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this is information on a product in full production. january 2016 docid15131 rev 9 1/133 spc560b54x, SPC560B60X, spc560b64x 32-bit mcu family built on the power architecture ? for automotive body electronics applications datasheet - production data features ? high performance 64 mhz e200z0h cpu ? 32-bit power architecture ? technology cpu ? up to 60 dmips operation ? variable length encoding (vle) ? memory ? up to 1.5 mb on-chip code flash with ecc ? 64 kb on-chip data flash with ecc ? up to 96 kb on-chip sram with ecc ? 8-entry mpu ? interrupts ? 16 priority levels ? non-maskable interrupt (nmi) ? up to 51 external interrupts lines including 27 wake-up lines ? 16-channel edma (linked to pits, dspi, adcs, emios, linflex and i 2 c) ? gpios: 77 (lqfp100), 121 (lqfp144) and 149 (lqfp176) ? timer units ? 8-channel 32-bit periodic interrupt timer ? 4-channel 32-bit system timer ? system watchdog timer ? real-time clock timer ? emios, 16-bit counter timed i/o units ? up to 64 channels with pwm/mc/ic/oc ? up to 10 counter basis ? adc diagnostic trigger via ctu ? one 10-bit and one 12-bit adc with up to 53 channels ? extendable to 81 channels ? individual conversion registers ? cross triggering unit (ctu) ? dedicated diagnostic module for lighting ? advanced pwm generation ? time-triggered diagnostics ? pwm-synchronized adc measurements ? on-chip can/uart bootstrap loader ? communications interfaces ? up to 6 flexcan (2.0b active) with 64 message buffers each ? up to 10 linflex/uart channels ? up to 6 buffered dspi channels ?i 2 c interface ? clock generation ? 4 to 16 mhz fast external crystal oscillator ? 32 khz slow external crystal oscillator ? 16 mhz fast internal rc oscillator ? 128 khz slow internal rc oscillator for low- power modes ? software-controlled fmpll ? clock monitoring unit ? low-power capabilities ? several low-power mode configurations ? ultra-low-power standby with rtc and communication ? fast wakeup schemes ? exhaustive debugging capability ? nexus 2+ interface on lbga208 package ? nexus 1 on all packages ? voltage supply ? single 5 v or 3.3 v supply ? on-chip voltage regulator ? external ballast resistor support ? lqfp100, lqfp144, and lqfp176 packages; lbga208 package for nexus2+ ? operating temperature range -40 to 125 c lqfp144 lqfp100 lqfp176 (20 x 20 x 1.4 mm) (24 x 24 x 1.4 mm) (14 x 14 x 1.4 mm) table 1. device summary package 768 kbyte code flash 1 mbyte code flash 1.5 mbyte code flash lqfp176 ? spc560b60l7 spc560b64l7 lqfp144 spc560b54l5 spc560b60l5 spc560b64l5 lqfp100 spc560b54l3 spc560b60l3 spc560b64l3 www.st.com
contents spc560b54x/6x 2/133 docid15131 rev 9 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 pad configuration during reset phases . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 pad configuration during standby mode exit . . . . . . . . . . . . . . . . . . . . . . 17 3.4 voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.6 system pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7 functional port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.8 nexus 2+ pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.1 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.2 nvusro register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.2.1 nvusro[pad3v5v] field description . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.2.2 nvusro[oscillator_margin] field description . . . . . . . . . . . . . . . 57 4.2.3 nvusro[watchdog_en] field description . . . . . . . . . . . . . . . . . . . . 57 4.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.4 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.5.1 external ballast resistor recommendations . . . . . . . . . . . . . . . . . . . . . . 61 4.5.2 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.5.3 power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.6 i/o pad electrical characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.6.1 i/o pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.6.2 i/o input dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.6.3 i/o output dc characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.6.4 output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
docid15131 rev 9 3/133 spc560b54x/6x contents 4 4.6.5 i/o pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.7 reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.8 power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 79 4.8.1 voltage regulator electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . 79 4.8.2 low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . 81 4.9 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.10 flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.10.1 program/erase characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.10.2 flash power supply dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.10.3 start-up/switch-off timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.11 electromagnetic compatibility (emc) characteristics . . . . . . . . . . . . . . . . 86 4.11.1 designing hardened software to avoid noise problems . . . . . . . . . . . . . 86 4.11.2 electromagnetic interference (emi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.11.3 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 87 4.12 fast external crystal oscillator (4 to 16 mhz) electrical c haracteristics . . 88 4.13 slow external crystal oscillator (32 khz) electrical characteristics . . . . . . 91 4.14 fmpll electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.15 fast internal rc oscillator (16 mhz) elec trical characteristics . . . . . . . . . 94 4.16 slow internal rc oscillator (128 khz) el ectrical characteristics . . . . . . . . 95 4.17 adc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.17.2 input impedance and adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.17.3 adc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.18 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 4.18.1 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 4.18.2 dspi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 4.18.3 nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.18.4 jtag characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 5 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 5.1 ecopack? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 5.2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 5.2.1 lqfp176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 5.2.2 lqfp144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 5.2.3 lqfp100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
contents spc560b54x/6x 4/133 docid15131 rev 9 5.2.4 lbga208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 appendix a abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
docid15131 rev 9 5/133 spc560b54x/6x list of tables 6 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. spc560b54/6x family comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. spc560b54/6x series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4. voltage supply pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. system pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6. functional port pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 7. nexus 2+ pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 8. parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 9. pad3v5v field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 10. oscillator_margin field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 11. watchdog_en field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 12. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 13. recommended operating conditions (3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 14. recommended operating conditions (5.0 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 15. lqfp thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 16. i/o input dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 17. i/o pull-up/pull-down dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 18. slow configuration output buffer electrical charac teristics . . . . . . . . . . . . . . . . . . . . . . . . 65 table 19. medium configuration output buffer electrical ch aracteristics . . . . . . . . . . . . . . . . . . . . . . 66 table 20. fast configuration output buffer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 67 table 21. output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 22. i/o supply segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 23. i/o consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 24. i/o weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 25. reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 26. voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 27. low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 28. power consumption on vdd_bv and vdd_hv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 29. program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 30. flash module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 31. flash read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 32. flash power supply dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 33. start-up time/switch-off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 34. emi radiated emission measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 35. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 36. latch-up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 37. crystal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 38. fast external crystal oscillator (4 to 16 mhz) electrical characteristics. . . . . . . . . . . . . . . . 90 table 39. crystal motional characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 40. slow external crystal oscillato r (32 khz) electrical characteristics . . . . . . . . . . . . . . . . . . . 93 table 41. fmpll electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 42. fast internal rc oscillator (16 mhz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 94 table 43. slow internal rc oscillator (128 khz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 95 table 44. adc input leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 45. adc_0 conversion characteristics (10-bit adc_0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 46. adc_1 conversion characteristics (12-bit adc_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 47. on-chip peripherals current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 48. dspi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
list of tables spc560b54x/6x 6/133 docid15131 rev 9 table 49. nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 50. jtag characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 51. lqfp176 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 52. lqfp144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 53. lqfp100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 54. lbga208 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 55. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 56. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
docid15131 rev 9 7/133 spc560b54x/6x list of figures 7 list of figures figure 1. spc560b54/6x block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2. lqfp176 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3. lqfp144 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4. lqfp100 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 5. lbga208 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. i/o input dc electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 figure 7. start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 8. noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 9. voltage regulator capacitance connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 10. low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 11. crystal oscillator and resonato r connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 12. fast external crystal oscillato r (4 to 16 mhz) timing diagram . . . . . . . . . . . . . . . . . . . . . . . 90 figure 13. crystal oscillator and resonato r connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 14. equivalent circuit of a quartz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 15. slow external crystal oscillato r (32 khz) timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 16. adc_0 characteristic and error de finitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 figure 17. input equivalent circuit (preci se channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 18. input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 19. transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 20. spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 21. adc_1 characteristic and error de finitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 22. dspi classic spi timing ? master, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 23. dspi classic spi timing ? master, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 24. dspi classic spi timing ? slave, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 25. dspi classic spi timing ? slave, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 26. dspi modified transfer format timing ? master, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . 113 figure 27. dspi modified transfer format timing ? master, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . 114 figure 28. dspi modified transfer format timing ? slave, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 29. dspi modified transfer format timing ? slave, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 30. dspi pcs strobe (pcss) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 15 figure 31. nexus tdi, tms, tdo timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 32. timing diagram ? jtag boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 33. lqfp176 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 34. lqfp144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 35. lqfp100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 36. lbga208 package mechanical dr awing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 37. commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 26
introduction spc560b54x/6x 8/133 docid15131 rev 9 1 introduction 1.1 document overview this document describes the features of the family and options available within the family members, and highlights important electrical and physical characteri stics of the device. 1.2 description this family of 32-bit system -on-chip (soc) microcontrollers is the latest achievement in integrated automotive application controllers . it belongs to an expanding family of automotive-focused products designed to ad dress the next wave of body electronics applications within the vehicle. the advanced and cost-efficient e200z0h host processor core of this automotive controller family complies with the power architecture technology and only implements the vle (variable-length encoding) apu (auxiliary processor un it), providing impr oved code density. it operates at speeds of up to 64 mhz and offe rs high performance pr ocessing optimized for low power consumption. it capitalizes on the av ailable development infrastructure of current power architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. table 2. spc560b54/6x family comparison (1) feature spc560b54 spc560b60 spc560b64 cpu e200z0h execution speed (2) up to 64 mhz code flash memory 768 kb 1 mb 1.5 mb data flash memory 64 (4 ? 16) kb sram 64 kb 80 kb 96 kb mpu 8-entry edma 16 ch 10-bit adc yes dedicated (3) 7 ch 15 ch 7 ch 15 ch 29 ch 7 ch 15 ch 29 ch 29 ch shared with 12-bit adc 19 ch 12-bit adc yes dedicated (4) 5 ch shared with 10-bit adc 19 ch total timer i/o (5) emios 37 ch, 16-bit 64 ch, 16-bit 37 ch, 16-bit 64 ch, 16-bit 64 ch, 16-bit 37 ch, 16-bit 64 ch,1 6-bit 64 ch, 16-bit 64 ch, 16-bit counter / opwm / icoc (6) 10 ch o(i)pwm / opwfmb / opwmcb / icoc (7) 7 ch o(i)pwm / icoc (8) 7 ch 14 ch 7 ch 14 ch 14 ch 7 ch 14 ch 14 ch 14 ch
docid15131 rev 9 9/133 spc560b54x/6x introduction 132 opwm / icoc (9) 13 ch 33 ch 13 ch 33 ch 33 ch 13 ch 33 ch 33 ch 33 ch sci (linflex) 4 8 4 8 10 4 8 10 10 spi (dspi) 3 5 3 5 6 3 5 6 6 can (flexcan) 6 i2c 1 32 khz oscillator yes gpio (10) 77 121 77 121 149 77 121 149 149 debug jtag n2+ package lqfp 100 lqfp 144 lqfp 100 lqfp 144 lqfp 176 lqfp 100 lqfp 144 lqfp 176 lbga208 (11) 1. feature set dependent on selected peripheral multiplexing; table shows example. 2. based on 125 ? c ambient operating temperature. 3. not shared with 12-bit adc, but possibl y shared with other alternate functions. 4. not shared with 10-bit adc, but possibl y shared with other alternate functions. 5. see the emios section of the chip reference manual fo r information on the channel configuration and functions. 6. each channel supports a range of modes including modulus counters, pwm generation, input capture, output compare. 7. each channel supports a range of modes including pwm gener ation with dead time, input capture, output compare. 8. each channel supports a range of modes including pwm generat ion, input capture, output compare, period and pulse width measurement. 9. each channel supports a range of modes including pwm generation, input capture, and output compare. 10. maximum i/o count based on multiplexing with peripherals. 11. lbga208 available only as development package for nexus2+. table 2. spc560b54/6x family comparison (1) (continued) feature spc560b54 spc560b60 spc560b64
block diagram spc560b54x/6x 10/133 docid15131 rev 9 2 block diagram figure 1 shows a top-level block diagram of the spc560b54/6x. figure 1. spc560b54/6x block diagram 6 ? dspi fmpll nexus 2+ nexus sram siu l reset control 96 kb external imux gpio & jtag pad control jtag port nexus port e200z0h interrupt requests 64-bit 2 ? 3 crossbar switch 6 ? flexcan peripheral bridge interrupt request interrupt request i/o clocks instructions data voltage regulator nmi swt pit stm nmi siul . . . intc i 2 c . . . 10 ? linflex 64 ch 29 ch 10-bit mpu cmu sram flash code flash 1.5 mb data flash 64 kb mc_pcu mc_me mc_cgm mc_rgm bam ctu rtc sscm (master) (master) (slave) (slave) (slave) controller controller legend: adc analog-to-digital converter bam boot assist module cmu clock monitor unit ctu cross triggering unit dspideserial serial peripheral interface ? ecsm error correction status module edma enhanced direct memory access emios enhanced modular input output system flash flash memory flexcan controller area network fmpll frequency-modulated phase-locked loop gpio general-purpose input/output i 2 c inter-integrated circuit bus imux internal multiplexer intc interrupt controller jtag jtag controller linflex serial communication interface (lin support) ? ? mc_cgm clock generation module mc_me mode entry module mc_pcu power control unit mc_rgm reset generation module mpu memory protection unit nmi non-maskable interrupt pit periodic interrupt timer rtc real-time clock siul system integration unit lite sram static random-access memory sscm system status configuration module stm system timer module swt software watchdog timer vreg voltage regulator wkpu wakeup unit xbar crossbar switch mpu ecsm from peripheral registers blocks adc emios 19 ch 10-bit/12-bit adc (master) . . . . . . . . . wkpu 5 ch 12-bit adc edma interrupt request with wakeup functionality
docid15131 rev 9 11/133 spc560b54x/6x block diagram 132 table 3 summarizes the functions of the bl ocks present on the spc560b54/6x. table 3. spc560b54/6x series block summary block function analog-to-digital converter (adc) converts analog voltages to digital values boot assist module (bam) a block of read-only memory containing vle code which is executed according to the boot mode of the device clock generation module (mc_cgm) provides logic and control required for the generation of system and peripheral clocks clock monitor unit (cmu) monitors clock s ource (internal and external) integrity cross triggering unit (ctu) enables synchronization of adc conversi ons with a timer event from the emios or from the pit crossbar switch (xbar) supports simultaneous connections between two master ports and three slave ports. the crossbar supports a 32-bit address bus width and a 64-bit data bus width. deserial serial peripheral interface (dspi) provides a synchronous serial interface for communication with external devices enhanced direct memory access (edma) performs complex data transfers with mi nimal intervention from a host processor via ? n ? programmable channels enhanced modular input output system (emios) provides the functionality to generate or measure events error correction status module (ecsm) provides a myriad of miscellaneous control functions for the device including program-visible information about configur ation and revision levels, a reset status register, wakeup control for exiting sleep modes, and optional features such as information on memory errors repo rted by error-correcting codes flash memory provides non-volatile storage for program code, constants and variables flexcan (controller area network) supports the standard can communications protocol frequency-modulated phase- locked loop (fmpll) generates high-speed system clocks and supports programmable frequency modulation inter-integrated circuit (i 2 c) bus two-wire bidirectional serial bus that pr ovides a simple and efficient method of data exchange between devices internal multiplexer (imux) siu subblock allows flexible mapping of peripheral inte rface on the different pins of the device interrupt controller (intc) provid es priority-based preemptive sc heduling of interrupt requests jtag controller (jtagc) provides the means to test chip functionality and connectivity while remaining transparent to system logi c when not in test mode linflex controller manages a high number of lin (local interconnect network protocol) messages efficiently with a minimum of cpu load memory protection unit (mpu) provides hardware access control for all memory references generated in a device
block diagram spc560b54x/6x 12/133 docid15131 rev 9 mode entry module (mc_me) provides a mechanism for controlling the device operational mode and mode transition sequences in all functional states; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications non-maskable interrupt (nmi) handles external events that must produce an immediate response, such as power down detection periodic interrupt timer (pit) produces periodic interrupts and triggers power control unit (mc_pcu) reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called ?power dom ains? which are controlled by the pcu real-time counter (rtc) a free running counter used for time keeping applications, the rtc can be configured to generate an interrupt at a predefined interval independent of the mode of operation (run mode or low-power mode) reset generation module (mc_rgm) centralizes reset sources and manages the device reset sequence of the device static random-access memory (sram) provides storage for program co de, constants, and variables system integration unit lite (siul) provides control over all the electrical pa d controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration system status and configuration module (sscm) provides system configuratio n and status data (such as memory size and status, device mode and security status), devic e identification data, debug status port enable and selection, and bus and peripheral abort enable/disable system timer module (stm) provides a set of output compare events to support autosar (automotive open system architecture) and operating system tasks software watchdog timer (swt) provides protection from runaway code wakeup unit (wkpu) the wakeup unit supports up to 27 exte rnal sources that can generate interrupts or wakeup events, of which 1 can cause non-maskable interrupt requests or wakeup events. table 3. spc560b54/6x series block summary (continued) block function
docid15131 rev 9 13/133 spc560b54x/6x package pinouts and signal descriptions 132 3 package pinouts and signal descriptions 3.1 package pinouts the available lqfp pinouts and the ballmap are provided in the following figures. for pin signal descriptions, please see table 6 . figure 2 shows the spc560b54/6x in the lqfp176 package. figure 2. lqfp176 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 pa[11] pa[10] pa[9] pa[8] pa[7] pe[13] pf[14] pf[15] vdd_hv vss_hv pg[0] pg[1] ph[3] ph[2] ph[1] ph[0] pg[12] pg[13] pa[3] pi[13] pi[12] pi[11] pi[10] pi[9] pi[8] pb[15] pd[15] pb[14] pd[14] pb[13] pd[13] pb[12] pd[12] vdd_hv_adc1 vss_hv_adc1 pb[11] pd[11] pd[10] pd[9] pb[7] pb[6] pb[5] vdd_hv_adc0 vss_hv_adc0 pb[3] pc[9] pc[14] pc[15] pj[4] vdd_hv vss_hv ph[15] ph[13] ph[14] pi[6] pi[7] pg[5] pg[4] pg[3] pg[2] pa[2] pe[0] pa[1] pe[1] pe[8] pe[9] pe[10] pa[0] pe[11] vss_hv vdd_hv vss_hv reset vss_lv vdd_lv vdd_bv pg[9] pg[8] pc[11] pc[10] pg[7] pg[6] pb[0] pb[1] pf[9] pf[8] pf[12] pc[6] pc[7] pf[10] pf[11] pa[15] pf[13] pa[14] pa[4] pa[13] pa[12] vdd_lv vss_lv xtal vss_hv extal vdd_hv pb[9] pb[8] pb[10] pf[0] pf[1] pf[2] pf[3] pf[4] pf[5] pf[6] pf[7] pj[3] pj[2] pj[1] pj[0] pi[15] pi[14] pd[0] pd[1] pd[2] pd[3] pd[4] pd[5] pd[6] pd[7] vdd_hv vss_hv pd[8] pb[4] pb[2] pc[8] pc[13] pc[12] pi[0] pi[1] pi[2] pi[3] pe[7] pe[6] ph[8] ph[7] ph[6] ph[5] ph[4] pe[5] pe[4] pc[4] pc[5] pe[3] pe[2] ph[9] pc[0] vss_lv vdd_lv vdd_hv vss_hv pc[1] ph[10] pa[6] pa[5] pc[2] pc[3] pi[4] pi[5] ph[12] ph[11] pg[11] pg[10] pe[15] pe[14] pg[15] pg[14] pe[12] lqfp176 to p v i e w
package pinouts and signal descriptions spc560b54x/6x 14/133 docid15131 rev 9 figure 3 shows the spc560b54/6x in the lqfp144 package. figure 3. lqfp144 pin configuration figure 4 shows the spc560b54/6x in the lqfp100 package. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 pb[3] pc[9] pc[14] pc[15] pg[5] pg[4] pg[3] pg[2] pa[2] pe[0] pa[1] pe[1] pe[8] pe[9] pe[10] pa[0] pe[11] vss_hv vdd_hv vss_hv reset vss_lv vdd_lv vdd_bv pg[9] pg[8] pc[11] pc[10] pg[7] pg[6] pb[0] pb[1] pf[9] pf[8] pf[12] pc[6] pa[11] pa[10] pa[9] pa[8] pa[7] pe[13] pf[14] pf[15] vdd_hv vss_hv pg[0] pg[1] ph[3] ph[2] ph[1] ph[0] pg[12] pg[13] pa[3] pb[15] pd[15] pb[14] pd[14] pb[13] pd[13] pb[12] vdd_hv_adc1 vss_hv_adc1 pd[11] pd[10] pd[9] pb[7] pb[6] pb[5] vdd_hv_adc0 vss_hv_adc0 pc[7] pf[10] pf[11] pa[15] pf[13] pa[14] pa[4] pa[13] pa[12] vdd_lv vss_lv xtal vss_hv extal vdd_hv pb[9] pb[8] pb[10] pf[0] pf[1] pf[2] pf[3] pf[4] pf[5] pf[6] pf[7] pd[0] pd[1] pd[2] pd[3] pd[4] pd[5] pd[6] pd[7] pd[8] pb[4] pb[2] pc[8] pc[13] pc[12] pe[7] pe[6] ph[8] ph[7] ph[6] ph[5] ph[4] pe[5] pe[4] pc[4] pc[5] pe[3] pe[2] ph[9] pc[0] vss_lv vdd_lv vdd_hv vss_hv pc[1] ph[10] pa[6] pa[5] pc[2] pc[3] pg[11] pg[10] pe[15] pe[14] pg[15] pg[14] pe[12] lqfp144 top view
docid15131 rev 9 15/133 spc560b54x/6x package pinouts and signal descriptions 132 figure 4. lqfp100 pin configuration figure 5 shows the spc560b54/6x in the lbga208 package. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 pb[3] pc[9] pc[14] pc[15] pa[2] pe[0] pa[1] pe[1] pe[8] pe[9] pe[10] pa[0] pe[11] vss_hv vdd_hv vss_hv reset vss_lv vdd_lv vdd_bv pc[11] pc[10] pb[0] pb[1] pc[6] pa[11] pa[10] pa[9] pa[8] pa[7] vdd_hv vss_hv pa[3] pb[15] pd[15] pb[14] pd[14] pb[13] pd[13] pb[12] vdd_hv_adc1 vss_hv_adc1 pd[11] pd[10] pd[9] pb[7] pb[6] pb[5] vdd_hv_adc0 vss_hv_adc0 pc[7] pa[15] pa[14] pa[4] pa[13] pa[12] vdd_lv vss_lv xtal vss_hv extal vdd_hv pb[9] pb[8] pb[10] pd[0] pd[1] pd[2] pd[3] pd[4] pd[5] pd[6] pd[7] pd[8] pb[4] pb[2] pc[8] pc[13] pc[12] pe[7] pe[6] pe[5] pe[4] pc[4] pc[5] pe[3] pe[2] ph[9] pc[0] vss_lv vdd_lv vdd_hv vss_hv pc[1] ph[10] pa[6] pa[5] pc[2] pc[3] pe[12] lqfp100 top view
package pinouts and signal descriptions spc560b54x/6x 16/133 docid15131 rev 9 3.2 pad configuration during reset phases all pads have a fixed configuration under reset. during the power-up phase, all pads are forced to tristate. after power-up phase, all pads are tristate with the following exceptions: ? pa[9] (fab) is pull-down. without external str ong pull-up the device starts fetching from flash. ? pa[8], pc[0] and ph[9:10] are in input weak pull-up when out of reset. ? reset pad is driven low by the device till 40 firc clock cycles after phase2 completion. minimum phase3 duration is 40 firc cycles. ? nexus output pads (mdo[n], mcko, evto, mseo) are forced to output. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a pc[8] pc[13] ph[15] pj[4] ph[8] ph[4] pc[5] pc[0] pi[0] pi[1] pc[2] pi[4] pe[15] ph[11] nc nc a b pc[9] pb[2] ph[13] pc[12] pe[6] ph[5] pc[4] ph[9] ph[10] pi[2] pc[3] pg[11] pg[15] pg[14] pa[11] pa[10] b c pc[14] vdd_h v pb[3] pe[7] ph[7] pe[5] pe[3] vss_lv pc[1] pi[3] pa[5] pi[5] pe[14] pe[12] pa[9] pa[8] c d ph[14] pi[6] pc[15] pi[7] ph[6] pe[4] pe[2] vdd_l v vdd_h v nc pa[6] ph[12] pg[10] pf[14] pe[13] pa[7] d e pg[4] pg[5] pg[3] pg[2] pg[1] pg[0] pf[15] vdd_h v e f pe[0] pa[2] pa[1] pe[1] ph[0] ph[1] ph[3] ph[2] f g pe[9] pe[8] pe[10] pa[0] vss_h v vss_h v vss_h v vss_h v vdd_h v pi[12] pi[13] mseo g h vss_hv pe[11] vdd_h v nc vss_h v vss_h v vss_h v vss_h v mdo3 mdo2 mdo0 mdo1 h j reset vss_lv nc nc vss_h v vss_h v vss_h v vss_h v pi[8] pi[9] pi[10] pi[11] j k evti nc vdd_b v vdd_l v vss_h v vss_h v vss_h v vss_h v vdd_h v_adc 1 pg[12] pa[3] pg[13] k l pg[9] pg[8] nc evto pb[15] pd[15] pd[14] pb[14] l m pg[7] pg[6] pc[10] pc[11] pb[13] pd[13] pd[12] pb[12] m n pb[1] pf[9] pb[0] vdd_h v pj[0] pa[4] vss_lv extal vdd_h v pf[0] pf[4] vss_h v_adc 1 pb[11] pd[10] pd[9] pd[11] n p pf[8] pj[3] pc[7] pj[2] pj[1] pa[14] vdd_l v xtal pb[10] pf[1] pf[5] pd[0] pd[3] vdd_h v_adc 0 pb[6] pb[7] p r pf[12] pc[6] pf[10] pf[11] vdd_h v pa[15] pa[13] pi[14] xtal32 pf[3] pf[7] pd[2] pd[4] pd[7] vss_h v_adc 0 pb[5] r t nc nc nc mcko nc pf[13] pa[12] pi[15] extal 32 pf[2] pf[6] pd[1] pd[5] pd[6] pd[8] pb[4] t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 note: the lbga208 is av ailable only as development package for nexus 2+. nc = not connected figure 5. lbga208 configuration
docid15131 rev 9 17/133 spc560b54x/6x package pinouts and signal descriptions 132 3.3 pad configuration during standby mode exit pad configuration (input buffer enable, pull enable) for low-power wakeup pads is controlled by both the siul and wkpu modules. during standby exit, all low power pads pa[0,1,2,4,15], pb[1,3,8,9,10] (a) , pc[7,9,11], pd[0,1], pe[0,9,11], pf[9,11,13] (b) , pg[3,5,7,9] (b) , pi[1,3] (c) are configured according to their respective configuration done in the wkpu module. all other pads will have t he same configuration as expected after a reset. the tdo pad has been moved into the standby domain in order to allow low-power debug handshaking in standby mode. however, no pull-resistor is active on the tdo pad while in standby mode. at this time the pad is configured as an input. when no debugger is connected the tdo pad is floating causing additional current consumption. to avoid the extra consumption tdo must be connected. an external pull-up resistor in the range of 47?100 kohms should be added betw een the tdo pin and vdd. only if the tdo pin is used as an application pin and a pull-up cannot be used should a pull-down resistor with the same value be used instead between the tdo pin and gnd. 3.4 voltage supply pins voltage supply pins are used to provide power to the device. three dedicated vdd_lv/vss_lv supply pairs are used for 1.2 v regulator stabilization. a. pb[8, 9] ports have wakeup functionality in all modes except standby. b. pf[9,11,13], pg[3,5,7,9], pi[1,3] are not available in the 100-pin lqfp. c. pi[1,3] are not available in the 144-pin lqfp. table 4. voltage supply pin descriptions port pin function pin number lqfp100 lqfp144 lqfp176 lbga208 vdd_hv digital supply voltage 15, 37, 70, 84 19, 51, 100, 123 6, 27, 59, 85, 124, 151 c2, d9, e16, g13, h3, n4, n9, r5 vss_hv digital ground 14, 16, 35, 69, 83 18, 20, 49, 99, 122 7, 26, 28, 57, 86, 123, 150 g7, g8, g9, g10, h7, h8, h9, h10, j7, j8, j9, j10, k7, k8, k9, k10 vdd_lv 1.2 v decoupling pins. decoupling capacitor must be connected between these pins and the nearest v ss_lv pin. (1) 19, 32, 85 23, 46, 124 31, 54, 152 d8, k4, p7 vss_lv 1.2 v decoupling pins. decoupling capacitor must be connected between these pins and the nearest v dd_lv pin. (1) 18, 33, 86 22, 47, 125 30, 55, 153 c8, j2, n7
package pinouts and signal descriptions spc560b54x/6x 18/133 docid15131 rev 9 3.5 pad types in the device the following types of pads are available for system pins and functional port pins: s = slow (d) m = medium (d) (e) f = fast (d) (e) i = input only with analog feature (d) j = input/output (?s? pad) with analog feature x = oscillator 3.6 system pins the system pins are listed in table 5 . vdd_bv internal regulator supply voltage 20 24 32 k3 vss_hv_adc0 reference ground and analog ground for the a/d converter 0 (10- bit) 51 73 89 r15 vdd_hv_adc0 reference voltage and analog supply for the a/d converter 0 (10- bit) 52 74 90 p14 vss_hv_adc1 reference ground and analog ground for the a/d converter 1 (12- bit) 59 81 98 n12 vdd_hv_adc1 reference voltage and analog supply for the a/d converter 1 (12- bit) 60 82 99 k13 1. a decoupling capacitor must be placed between each of the th ree vdd_lv/vss_lv supply pairs to ensure stable voltage (see the recommended operating condi tions in the device datasheet). table 4. voltage supply pi n descriptions (continued) port pin function pin number lqfp100 lqfp144 lqfp176 lbga208 d. see the i/o pad electrical characteristics in the chip datasheet for details. e. all medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium. the only exception is pc[1] which is in medium conf iguration by default (see the pcr.src description in the chip reference manual, pad configuration registers (pcr0?pcr148)).
docid15131 rev 9 19/133 spc560b54x/6x package pinouts and signal descriptions 132 3.7 functional port pins the functional port pins are listed in table 6 . table 5. system pin descriptions port pin function i/o direction pad type reset configuration pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (1) reset bidirectional reset with schmitt- trigger characteristics and noise filter. i/o m input weak pull-up after rgm phase2 and 40 firc cycles 17 21 29 j1 extal analog output of the oscillator amplifier circuit, when the oscillator is not in bypass mode. ? analog input for the clock generator when the oscillator is in bypass mode. i/o x tristate 36 50 58 n8 xtal analog input of the oscillator amplifier circuit. needs to be grounded if oscillator bypass mode is used. i x tristate 34 48 56 p8 1. lbga208 available only as dev elopment package for nexus2+.
package pinouts and signal descriptions spc560b54x/6x 20/133 docid15131 rev 9 table 6. functional port pin descriptions port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4) port a pa[0] pcr[0] af0 af1 af2 af3 ? gpio[0] e0uc[0] clkout e0uc[13] wkpu[19] (5) siul emios_0 mc_cgm emios_0 wkpu i/o i/o o i/o i m tristate 12 16 24 g4 pa[1] pcr[1] af0 af1 af2 af3 ? gpio[1] e0uc[1] nmi (6) ? wkpu[2] (5) siul emios_0 wkpu ? wkpu i/o i/o i ? i stristate 7 11 19 f3 pa[2] pcr[2] af0 af1 af2 af3 ? gpio[2] e0uc[2] ? ma[2] wkpu[3] (5) siul emios_0 ? adc_0 wkpu i/o i/o ? o i s tristate 5 9 17 f2 pa[3] pcr[3] af0 af1 af2 af3 ? ? gpio[3] e0uc[3] lin5tx cs4_1 eirq[0] adc1_s[0] siul emios_0 linflex_5 dspi_1 siul adc_1 i/o i/o o o i i j tristate 68 90 114 k15
spc560b54x/6x package pinouts and signal descriptions docid15131 rev 9 21/133 pa[4] pcr[4] af0 af1 af2 af3 ? ? gpio[4] e0uc[4] ? cs0_1 lin5rx wkpu[9] (5) siul emios_0 ? dspi_1 linflex_5 wkpu i/o i/o ? i/o i i s tristate 29 43 51 n6 pa[5] pcr[5] af0 af1 af2 af3 gpio[5] e0uc[5] lin4tx ? siul emios_0 linflex_4 ? i/o i/o o ? m tristate 79 118 146 c11 pa[6] pcr[6] af0 af1 af2 af3 ? ? gpio[6] e0uc[6] ? cs1_1 eirq[1] lin4rx siul emios_0 ? dspi_1 siul linflex_4 i/o i/o ? o i i s tristate 80 119 147 d11 pa[7] pcr[7] af0 af1 af2 af3 ? ? gpio[7] e0uc[7] lin3tx ? eirq[2] adc1_s[1] siul emios_0 linflex_3 ? siul adc_1 i/o i/o o ? i i j tristate 71 104 128 d16 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
package pinouts and signal descriptions spc560b54x/6x 22/133 docid15131 rev 9 pa[8] pcr[8] af0 af1 af2 af3 ? n/a (7) ? gpio[8] e0uc[8] e0uc[14] ? eirq[3] abs[0] lin3rx siul emios_0 emios_0 ? siul bam linflex_3 i/o i/o i/o ? i i i s input, weak pull- up 72 105 129 c16 pa[9] pcr[9] af0 af1 af2 af3 n/a (7) gpio[9] e0uc[9] ? cs2_1 fab siul emios_0 ? dspi_1 bam i/o i/o ? o i s pull- down 73 106 130 c15 pa[10] pcr[10] af0 af1 af2 af3 ? gpio[10] e0uc[10] sda lin2tx adc1_s[2] siul emios_0 i 2 c_0 linflex_2 adc_1 i/o i/o i/o o i j tristate 74 107 131 b16 pa[11] pcr[11] af0 af1 af2 af3 ? ? ? gpio[11] e0uc[11] scl ? eirq[16] lin2rx adc1_s[3] siul emios_0 i 2 c_0 ? siul linflex_2 adc_1 i/o i/o i/o ? i i i j tristate 75 108 132 b15 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
spc560b54x/6x package pinouts and signal descriptions docid15131 rev 9 23/133 pa[12] pcr[12] af0 af1 af2 af3 ? ? gpio[12] ? e0uc[28] cs3_1 eirq[17] sin_0 siul ? emios_0 dspi_1 siul dspi_0 i/o ? i/o o i i s tristate 31 45 53 t7 pa[13] pcr[13] af0 af1 af2 af3 gpio[13] sout_0 e0uc[29] ? siul dspi_0 emios_0 ? i/o o i/o ? m tristate 30 44 52 r7 pa[14] pcr[14] af0 af1 af2 af3 ? gpio[14] sck_0 cs0_0 e0uc[0] eirq[4] siul dspi_0 dspi_0 emios_0 siul i/o i/o i/o i/o i m tristate 28 42 50 p6 pa[15] pcr[15] af0 af1 af2 af3 ? gpio[15] cs0_0 sck_0 e0uc[1] wkpu[10] (5) siul dspi_0 dspi_0 emios_0 wkpu i/o i/o i/o i/o i m tristate 27 40 48 r6 port b pb[0] pcr[16] af0 af1 af2 af3 gpio[16] can0tx e0uc[30] lin0tx siul flexcan_0 emios_0 linflex_0 i/o o i/o o m tristate 23 31 39 n3 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
package pinouts and signal descriptions spc560b54x/6x 24/133 docid15131 rev 9 pb[1] pcr[17] af0 af1 af2 af3 ? ? ? gpio[17] ? e0uc[31] ? wkpu[4] (5) can0rx lin0rx siul ? emios_0 ? wkpu flexcan_0 linflex_0 i/o ? i/o ? i i i s tristate 24 32 40 n1 pb[2] pcr[18] af0 af1 af2 af3 gpio[18] lin0tx sda e0uc[30] siul linflex_0 i 2 c_0 emios_0 i/o o i/o i/o m tristate 100 144 176 b2 pb[3] pcr[19] af0 af1 af2 af3 ? ? gpio[19] e0uc[31] scl ? wkpu[11] (5) lin0rx siul emios_0 i 2 c_0 ? wkpu linflex_0 i/o i/o i/o ? i i stristate111c3 pb[4] pcr[20] af0 af1 af2 af3 ? ? ? ? ? ? ? adc0_p[0] adc1_p[0] gpio[20] ? ? ? ? adc_0 adc_1 siul ? ? ? ? i i i itristate 50 72 88 t16 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
spc560b54x/6x package pinouts and signal descriptions docid15131 rev 9 25/133 pb[5] pcr[21] af0 af1 af2 af3 ? ? ? ? ? ? ? adc0_p[1] adc1_p[1] gpio[21] ? ? ? ? adc_0 adc_1 siul ? ? ? ? i i i itristate 53 75 91 r16 pb[6] pcr[22] af0 af1 af2 af3 ? ? ? ? ? ? ? adc0_p[2] adc1_p[2] gpio[22] ? ? ? ? adc_0 adc_1 siul ? ? ? ? i i i itristate 54 76 92 p15 pb[7] pcr[23] af0 af1 af2 af3 ? ? ? ? ? ? ? adc0_p[3] adc1_p[3] gpio[23] ? ? ? ? adc_0 adc_1 siul ? ? ? ? i i i itristate 55 77 93 p16 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
package pinouts and signal descriptions spc560b54x/6x 26/133 docid15131 rev 9 pb[8] pcr[24] af0 af1 af2 af3 ? ? ? ? gpio[24] ? ? ? osc32k_xtal (8) wkpu[25] (5) adc0_s[0] adc1_s[4] siul ? ? ? osc32k wkpu adc_0 adc_1 i ? ? ? ? i (9) i i i ? 39 53 61 r9 pb[9] pcr[25] af0 af1 af2 af3 ? ? ? ? gpio[25] ? ? ? osc32k_extal (8) wkpu[26] (5) adc0_s[1] adc1_s[5] siul ? ? ? osc32k wkpu adc_0 adc_1 i ? ? ? ? i (9) i i i ? 38 52 60 t9 pb[10] pcr[26] af0 af1 af2 af3 ? ? ? gpio[26] ? ? ? wkpu[8] (5) adc0_s[2] adc1_s[6] siul ? ? ? wkpu adc_0 adc_1 i/o ? ? ? i i i j tristate 40 54 62 p9 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
spc560b54x/6x package pinouts and signal descriptions docid15131 rev 9 27/133 pb[11] pcr[27] af0 af1 af2 af3 ? gpio[27] e0uc[3] ? cs0_0 adc0_s[3] siul emios_0 ? dspi_0 adc_0 i/o i/o ? i/o i jtristate ? ? 97 n13 pb[12] pcr[28] af0 af1 af2 af3 ? gpio[28] e0uc[4] ? cs1_0 adc0_x[0] siul emios_0 ? dspi_0 adc_0 i/o i/o ? o i j tristate 61 83 101 m16 pb[13] pcr[29] af0 af1 af2 af3 ? gpio[29] e0uc[5] ? cs2_0 adc0_x[1] siul emios_0 ? dspi_0 adc_0 i/o i/o ? o i j tristate 63 85 103 m13 pb[14] pcr[30] af0 af1 af2 af3 ? gpio[30] e0uc[6] ? cs3_0 adc0_x[2] siul emios_0 ? dspi_0 adc_0 i/o i/o ? o i j tristate 65 87 105 l16 pb[15] pcr[31] af0 af1 af2 af3 ? gpio[31] e0uc[7] ? cs4_0 adc0_x[3] siul emios_0 ? dspi_0 adc_0 i/o i/o ? o i j tristate 67 89 107 l13 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
package pinouts and signal descriptions spc560b54x/6x 28/133 docid15131 rev 9 port c pc[0] (10) pcr[32] af0 af1 af2 af3 gpio[32] ? tdi ? siul ? jtagc ? i/o ? i ? m input, weak pull- up 87 126 154 a8 pc[1] (10) pcr[33] af0 af1 af2 af3 gpio[33] ? tdo ? siul ? jtagc ? i/o ? o ? f (11) tristate 82 121 149 c9 pc[2] pcr[34] af0 af1 af2 af3 ? gpio[34] sck_1 can4tx debug[0] eirq[5] siul dspi_1 flexcan_4 sscm siul i/o i/o o o i m tristate 78 117 145 a11 pc[3] pcr[35] af0 af1 af2 af3 ? ? ? gpio[35] cs0_1 ma[0] debug[1] eirq[6] can1rx can4rx siul dspi_1 adc_0 sscm siul flexcan_1 flexcan_4 i/o i/o o o i i i s tristate 77 116 144 b11 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
spc560b54x/6x package pinouts and signal descriptions docid15131 rev 9 29/133 pc[4] pcr[36] af0 af1 af2 af3 ? ? ? gpio[36] e1uc[31] ? debug[2] eirq[18] sin_1 can3rx siul emios_1 ? sscm siul dspi_1 flexcan_3 i/o i/o ? o i i i m tristate 92 131 159 b7 pc[5] pcr[37] af0 af1 af2 af3 ? gpio[37] sout_1 can3tx debug[3] eirq[7] siul dspi_1 flexcan_3 sscm siul i/o o o o i m tristate 91 130 158 a7 pc[6] pcr[38] af0 af1 af2 af3 gpio[38] lin1tx e1uc[28] debug[4] siul linflex_1 emios_1 sscm i/o o i/o o s tristate 25 36 44 r2 pc[7] pcr[39] af0 af1 af2 af3 ? ? gpio[39] ? e1uc[29] debug[5] lin1rx wkpu[12] (5) siul ? emios_1 sscm linflex_1 wkpu i/o ? i/o o i i s tristate 26 37 45 p3 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
package pinouts and signal descriptions spc560b54x/6x 30/133 docid15131 rev 9 pc[8] pcr[40] af0 af1 af2 af3 gpio[40] lin2tx e0uc[3] debug[6] siul linflex_2 emios_0 sscm i/o o i/o o s tristate 99 143 175 a1 pc[9] pcr[41] af0 af1 af2 af3 ? ? gpio[41] ? e0uc[7] debug[7] wkpu[13] (5) lin2rx siul ? emios_0 sscm wkpu linflex_2 i/o ? i/o o i i stristate222b1 pc[10] pcr[42] af0 af1 af2 af3 gpio[42] can1tx can4tx ma[1] siul flexcan_1 flexcan_4 adc_0 i/o o o o m tristate 22 28 36 m3 pc[11] pcr[43] af0 af1 af2 af3 ? ? ? gpio[43] ? ? ma[2] wkpu[5] (5) can1rx can4rx siul ? ? adc_0 wkpu flexcan_1 flexcan_4 i/o ? ? o i i i s tristate 21 27 35 m4 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
spc560b54x/6x package pinouts and signal descriptions docid15131 rev 9 31/133 pc[12] pcr[44] af0 af1 af2 af3 ? ? gpio[44] e0uc[12] ? ? eirq[19] sin_2 siul emios_0 ? ? siul dspi_2 i/o i/o ? ? i i m tristate 97 141 173 b4 pc[13] pcr[45] af0 af1 af2 af3 gpio[45] e0uc[13] sout_2 ? siul emios_0 dspi_2 ? i/o i/o o ? s tristate 98 142 174 a2 pc[14] pcr[46] af0 af1 af2 af3 ? gpio[46] e0uc[14] sck_2 ? eirq[8] siul emios_0 dspi_2 ? siul i/o i/o i/o ? i stristate333c1 pc[15] pcr[47] af0 af1 af2 af3 ? gpio[47] e0uc[15] cs0_2 ? eirq[20] siul emios_0 dspi_2 ? siul i/o i/o i/o ? i mtristate444d3 port d table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
package pinouts and signal descriptions spc560b54x/6x 32/133 docid15131 rev 9 pd[0] pcr[48] af0 af1 af2 af3 ? ? ? gpio[48] ? ? ? wkpu[27] (5) adc0_p[4] adc1_p[4] siul ? ? ? wkpu adc_0 adc_1 i ? ? ? i i i itristate 41 63 77 p12 pd[1] pcr[49] af0 af1 af2 af3 ? ? ? gpio[49] ? ? ? wkpu[28] (5) adc0_p[5] adc1_p[5] siul ? ? ? wkpu adc_0 adc_1 i ? ? ? i i i itristate 42 64 78 t12 pd[2] pcr[50] af0 af1 af2 af3 ? ? gpio[50] ? ? ? adc0_p[6] adc1_p[6] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate 43 65 79 r12 pd[3] pcr[51] af0 af1 af2 af3 ? ? gpio[51] ? ? ? adc0_p[7] adc1_p[7] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate 44 66 80 p13 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
spc560b54x/6x package pinouts and signal descriptions docid15131 rev 9 33/133 pd[4] pcr[52] af0 af1 af2 af3 ? ? gpio[52] ? ? ? adc0_p[8] adc1_p[8] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate 45 67 81 r13 pd[5] pcr[53] af0 af1 af2 af3 ? ? gpio[53] ? ? ? adc0_p[9] adc1_p[9] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate 46 68 82 t13 pd[6] pcr[54] af0 af1 af2 af3 ? ? gpio[54] ? ? ? adc0_p[10] adc1_p[10] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate 47 69 83 t14 pd[7] pcr[55] af0 af1 af2 af3 ? ? gpio[55] ? ? ? adc0_p[11] adc1_p[11] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate 48 70 84 r14 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
package pinouts and signal descriptions spc560b54x/6x 34/133 docid15131 rev 9 pd[8] pcr[56] af0 af1 af2 af3 ? ? gpio[56] ? ? ? adc0_p[12] adc1_p[12] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate 49 71 87 t15 pd[9] pcr[57] af0 af1 af2 af3 ? ? gpio[57] ? ? ? adc0_p[13] adc1_p[13] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate 56 78 94 n15 pd[10] pcr[58] af0 af1 af2 af3 ? ? gpio[58] ? ? ? adc0_p[14] adc1_p[14] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate 57 79 95 n14 pd[11] pcr[59] af0 af1 af2 af3 ? ? gpio[59] ? ? ? adc0_p[15] adc1_p[15] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate 58 80 96 n16 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
spc560b54x/6x package pinouts and signal descriptions docid15131 rev 9 35/133 pd[12] pcr[60] af0 af1 af2 af3 ? gpio[60] cs5_0 e0uc[24] ? adc0_s[4] siul dspi_0 emios_0 ? adc_0 i/o o i/o ? i j tristate ? ? 100 m15 pd[13] pcr[61] af0 af1 af2 af3 ? gpio[61] cs0_1 e0uc[25] ? adc0_s[5] siul dspi_1 emios_0 ? adc_0 i/o i/o i/o ? i j tristate 62 84 102 m14 pd[14] pcr[62] af0 af1 af2 af3 ? gpio[62] cs1_1 e0uc[26] ? adc0_s[6] siul dspi_1 emios_0 ? adc_0 i/o o i/o ? i j tristate 64 86 104 l15 pd[15] pcr[63] af0 af1 af2 af3 ? gpio[63] cs2_1 e0uc[27] ? adc0_s[7] siul dspi_1 emios_0 ? adc_0 i/o o i/o ? i j tristate 66 88 106 l14 port e table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
package pinouts and signal descriptions spc560b54x/6x 36/133 docid15131 rev 9 pe[0] pcr[64] af0 af1 af2 af3 ? ? gpio[64] e0uc[16] ? ? wkpu[6] (5) can5rx siul emios_0 ? ? wkpu flexcan_5 i/o i/o ? ? i i s tristate 6 10 18 f1 pe[1] pcr[65] af0 af1 af2 af3 gpio[65] e0uc[17] can5tx ? siul emios_0 flexcan_5 ? i/o i/o o ? m tristate 8 12 20 f4 pe[2] pcr[66] af0 af1 af2 af3 ? ? gpio[66] e0uc[18] ? ? eirq[21] sin_1 siul emios_0 ? ? siul dspi_1 i/o i/o ? ? i i m tristate 89 128 156 d7 pe[3] pcr[67] af0 af1 af2 af3 gpio[67] e0uc[19] sout_1 ? siul emios_0 dspi_1 ? i/o i/o o ? m tristate 90 129 157 c7 pe[4] pcr[68] af0 af1 af2 af3 ? gpio[68] e0uc[20] sck_1 ? eirq[9] siul emios_0 dspi_1 ? siul i/o i/o i/o ? i m tristate 93 132 160 d6 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
spc560b54x/6x package pinouts and signal descriptions docid15131 rev 9 37/133 pe[5] pcr[69] af0 af1 af2 af3 gpio[69] e0uc[21] cs0_1 ma[2] siul emios_0 dspi_1 adc_0 i/o i/o i/o o m tristate 94 133 161 c6 pe[6] pcr[70] af0 af1 af2 af3 ? gpio[70] e0uc[22] cs3_0 ma[1] eirq[22] siul emios_0 dspi_0 adc_0 siul i/o i/o o o i m tristate 95 139 167 b5 pe[7] pcr[71] af0 af1 af2 af3 ? gpio[71] e0uc[23] cs2_0 ma[0] eirq[23] siul emios_0 dspi_0 adc_0 siul i/o i/o o o i m tristate 96 140 168 c4 pe[8] pcr[72] af0 af1 af2 af3 gpio[72] can2tx e0uc[22] can3tx siul flexcan_2 emios_0 flexcan_3 i/o o i/o o m tristate 9 13 21 g2 pe[9] pcr[73] af0 af1 af2 af3 ? ? ? gpio[73] ? e0uc[23] ? wkpu[7] (5) can2rx can3rx siul ? emios_0 ? wkpu flexcan_2 flexcan_3 i/o ? i/o ? i i i s tristate 10 14 22 g1 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
package pinouts and signal descriptions spc560b54x/6x 38/133 docid15131 rev 9 pe[10] pcr[74] af0 af1 af2 af3 ? gpio[74] lin3tx cs3_1 e1uc[30] eirq[10] siul linflex_3 dspi_1 emios_1 siul i/o o o i/o i s tristate 11 15 23 g3 pe[11] pcr[75] af0 af1 af2 af3 ? ? gpio[75] e0uc[24] cs4_1 ? lin3rx wkpu[14] (5) siul emios_0 dspi_1 ? linflex_3 wkpu i/o i/o o ? i i s tristate 13 17 25 h2 pe[12] pcr[76] af0 af1 af2 af3 ? ? ? gpio[76] ? e1uc[19] (12) ? eirq[11] sin_2 adc1_s[7] siul ? emios_1 ? siul dspi_2 adc_1 i/o ? i/o ? i i i j tristate 76 109 133 c14 pe[13] pcr[77] af0 af1 af2 af3 gpio[77] sout_2 e1uc[20] ? siul dspi_2 emios_1 ? i/o o i/o ? s tristate ? 103 127 d15 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
spc560b54x/6x package pinouts and signal descriptions docid15131 rev 9 39/133 pe[14] pcr[78] af0 af1 af2 af3 ? gpio[78] sck_2 e1uc[21] ? eirq[12] siul dspi_2 emios_1 ? siul i/o i/o i/o ? i s tristate ? 112 136 c13 pe[15] pcr[79] af0 af1 af2 af3 gpio[79] cs0_2 e1uc[22] ? siul dspi_2 emios_1 ? i/o i/o i/o ? m tristate ? 113 137 a13 port f pf[0] pcr[80] af0 af1 af2 af3 ? gpio[80] e0uc[10] cs3_1 ? adc0_s[8] siul emios_0 dspi_1 ? adc_0 i/o i/o o ? i j tristate ? 55 63 n10 pf[1] pcr[81] af0 af1 af2 af3 ? gpio[81] e0uc[11] cs4_1 ? adc0_s[9] siul emios_0 dspi_1 ? adc_0 i/o i/o o ? i j tristate ? 56 64 p10 pf[2] pcr[82] af0 af1 af2 af3 ? gpio[82] e0uc[12] cs0_2 ? adc0_s[10] siul emios_0 dspi_2 ? adc_0 i/o i/o i/o ? i j tristate ? 57 65 t10 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
package pinouts and signal descriptions spc560b54x/6x 40/133 docid15131 rev 9 pf[3] pcr[83] af0 af1 af2 af3 ? gpio[83] e0uc[13] cs1_2 ? adc0_s[11] siul emios_0 dspi_2 ? adc_0 i/o i/o o ? i j tristate ? 58 66 r10 pf[4] pcr[84] af0 af1 af2 af3 ? gpio[84] e0uc[14] cs2_2 ? adc0_s[12] siul emios_0 dspi_2 ? adc_0 i/o i/o o ? i j tristate ? 59 67 n11 pf[5] pcr[85] af0 af1 af2 af3 ? gpio[85] e0uc[22] cs3_2 ? adc0_s[13] siul emios_0 dspi_2 ? adc_0 i/o i/o o ? i j tristate ? 60 68 p11 pf[6] pcr[86] af0 af1 af2 af3 ? gpio[86] e0uc[23] cs1_1 ? adc0_s[14] siul emios_0 dspi_1 ? adc_0 i/o i/o o ? i j tristate ? 61 69 t11 pf[7] pcr[87] af0 af1 af2 af3 ? gpio[87] ? cs2_1 ? adc0_s[15] siul ? dspi_1 ? adc_0 i/o ? o ? i j tristate ? 62 70 r11 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
spc560b54x/6x package pinouts and signal descriptions docid15131 rev 9 41/133 pf[8] pcr[88] af0 af1 af2 af3 gpio[88] can3tx cs4_0 can2tx siul flexcan_3 dspi_0 flexcan_2 i/o o o o m tristate ? 34 42 p1 pf[9] pcr[89] af0 af1 af2 af3 ? ? ? gpio[89] e1uc[1] cs5_0 ? wkpu[22] (5) can2rx can3rx siul emios_1 dspi_0 ? wkpu flexcan_2 flexcan_3 i/o i/o o ? i i i s tristate ? 33 41 n2 pf[10] pcr[90] af0 af1 af2 af3 gpio[90] cs1_0 lin4tx e1uc[2] siul dspi_0 linflex_4 emios_1 i/o o o i/o m tristate ? 38 46 r3 pf[11] pcr[91] af0 af1 af2 af3 ? ? gpio[91] cs2_0 e1uc[3] ? wkpu[15] (5) lin4rx siul dspi_0 emios_1 ? wkpu linflex_4 i/o o i/o ? i i s tristate ? 39 47 r4 pf[12] pcr[92] af0 af1 af2 af3 gpio[92] e1uc[25] lin5tx ? siul emios_1 linflex_5 ? i/o i/o o ? m tristate ? 35 43 r1 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
package pinouts and signal descriptions spc560b54x/6x 42/133 docid15131 rev 9 pf[13] pcr[93] af0 af1 af2 af3 ? ? gpio[93] e1uc[26] ? ? wkpu[16] (5) lin5rx siul emios_1 ? ? wkpu linflex_5 i/o i/o ? ? i i s tristate ? 41 49 t6 pf[14] pcr[94] af0 af1 af2 af3 gpio[94] can4tx e1uc[27] can1tx siul flexcan_4 emios_1 flexcan_1 i/o o i/o o m tristate ? 102 126 d14 pf[15] pcr[95] af0 af1 af2 af3 ? ? ? gpio[95] e1uc[4] ? ? eirq[13] can1rx can4rx siul emios_1 ? ? siul flexcan_1 flexcan_4 i/o i/o ? ? i i i s tristate ? 101 125 e15 port g pg[0] pcr[96] af0 af1 af2 af3 gpio[96] can5tx e1uc[23] ? siul flexcan_5 emios_1 ? i/o o i/o ? m tristate ? 98 122 e14 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
spc560b54x/6x package pinouts and signal descriptions docid15131 rev 9 43/133 pg[1] pcr[97] af0 af1 af2 af3 ? ? gpio[97] ? e1uc[24] ? eirq[14] can5rx siul ? emios_1 ? siul flexcan_5 i/o ? i/o ? i i s tristate ? 97 121 e13 pg[2] pcr[98] af0 af1 af2 af3 gpio[98] e1uc[11] sout_3 ? siul emios_1 dspi_3 ? i/o i/o o ? m tristate ? 8 16 e4 pg[3] pcr[99] af0 af1 af2 af3 ? gpio[99] e1uc[12] cs0_3 ? wkpu[17] (5) siul emios_1 dspi_3 ? wkpu i/o i/o i/o ? i s tristate ? 7 15 e3 pg[4] pcr[100] af0 af1 af2 af3 gpio[100] e1uc[13] sck_3 ? siul emios_1 dspi_3 ? i/o i/o i/o ? m tristate ? 6 14 e1 pg[5] pcr[101] af0 af1 af2 af3 ? ? gpio[101] e1uc[14] ? ? wkpu[18] (5) sin_3 siul emios_1 ? ? wkpu dspi_3 i/o i/o ? ? i i s tristate ? 5 13 e2 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
package pinouts and signal descriptions spc560b54x/6x 44/133 docid15131 rev 9 pg[6] pcr[102] af0 af1 af2 af3 gpio[102] e1uc[15] lin6tx ? siul emios_1 linflex_6 ? i/o i/o o ? m tristate ? 30 38 m2 pg[7] pcr[103] af0 af1 af2 af3 ? ? gpio[103] e1uc[16] e1uc[30] ? wkpu[20] (5) lin6rx siul emios_1 emios_1 ? wkpu linflex_6 i/o i/o i/o ? i i s tristate ? 29 37 m1 pg[8] pcr[104] af0 af1 af2 af3 ? gpio[104] e1uc[17] lin7tx cs0_2 eirq[15] siul emios_1 linflex_7 dspi_2 siul i/o i/o o i/o i s tristate ? 26 34 l2 pg[9] pcr[105] af0 af1 af2 af3 ? ? gpio[105] e1uc[18] ? sck_2 wkpu[21] (5) lin7rx siul emios_1 ? dspi_2 wkpu linflex_7 i/o i/o ? i/o i i s tristate ? 25 33 l1 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
spc560b54x/6x package pinouts and signal descriptions docid15131 rev 9 45/133 pg[10] pcr[106] af0 af1 af2 af3 ? gpio[106] e0uc[24] e1uc[31] ? sin_4 siul emios_0 emios_1 ? dspi_4 i/o i/o i/o ? i s tristate ? 114 138 d13 pg[11] pcr[107] af0 af1 af2 af3 gpio[107] e0uc[25] cs0_4 ? siul emios_0 dspi_4 ? i/o i/o i/o ? m tristate ? 115 139 b12 pg[12] pcr[108] af0 af1 af2 af3 gpio[108] e0uc[26] sout_4 ? siul emios_0 dspi_4 ? i/o i/o o ? m tristate ? 92 116 k14 pg[13] pcr[109] af0 af1 af2 af3 gpio[109] e0uc[27] sck_4 ? siul emios_0 dspi_4 ? i/o i/o i/o ? m tristate ? 91 115 k16 pg[14] pcr[110] af0 af1 af2 af3 gpio[110] e1uc[0] lin8tx ? siul emios_1 linflex_8 ? i/o i/o o ? s tristate ? 110 134 b14 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
package pinouts and signal descriptions spc560b54x/6x 46/133 docid15131 rev 9 pg[15] pcr[111] af0 af1 af2 af3 ? gpio[111] e1uc[1] ? ? lin8rx siul emios_1 ? ? linflex_8 i/o i/o ? ? i m tristate ? 111 135 b13 port h ph[0] pcr[112] af0 af1 af2 af3 ? gpio[112] e1uc[2] ? ? sin_1 siul emios_1 ? ? dspi_1 i/o i/o ? ? i m tristate ? 93 117 f13 ph[1] pcr[113] af0 af1 af2 af3 gpio[113] e1uc[3] sout_1 ? siul emios_1 dspi_1 ? i/o i/o o ? m tristate ? 94 118 f14 ph[2] pcr[114] af0 af1 af2 af3 gpio[114] e1uc[4] sck_1 ? siul emios_1 dspi_1 ? i/o i/o i/o ? m tristate ? 95 119 f16 ph[3] pcr[115] af0 af1 af2 af3 gpio[115] e1uc[5] cs0_1 ? siul emios_1 dspi_1 ? i/o i/o i/o ? m tristate ? 96 120 f15 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
spc560b54x/6x package pinouts and signal descriptions docid15131 rev 9 47/133 ph[4] pcr[116] af0 af1 af2 af3 gpio[116] e1uc[6] ? ? siul emios_1 ? ? i/o i/o ? ? m tristate ? 134 162 a6 ph[5] pcr[117] af0 af1 af2 af3 gpio[117] e1uc[7] ? ? siul emios_1 ? ? i/o i/o ? ? s tristate ? 135 163 b6 ph[6] pcr[118] af0 af1 af2 af3 gpio[118] e1uc[8] ? ma[2] siul emios_1 ? adc_0 i/o i/o ? o m tristate ? 136 164 d5 ph[7] pcr[119] af0 af1 af2 af3 gpio[119] e1uc[9] cs3_2 ma[1] siul emios_1 dspi_2 adc_0 i/o i/o o o m tristate ? 137 165 c5 ph[8] pcr[120] af0 af1 af2 af3 gpio[120] e1uc[10] cs2_2 ma[0] siul emios_1 dspi_2 adc_0 i/o i/o o o m tristate ? 138 166 a5 ph[9] (10) pcr[121] af0 af1 af2 af3 gpio[121] ? tck ? siul ? jtagc ? i/o ? i ? s input, weak pull- up 88 127 155 b8 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
package pinouts and signal descriptions spc560b54x/6x 48/133 docid15131 rev 9 ph[10] (10) pcr[122] af0 af1 af2 af3 gpio[122] ? tms ? siul ? jtagc ? i/o ? i ? m input, weak pull- up 81 120 148 b9 ph[11] pcr[123] af0 af1 af2 af3 gpio[123] sout_3 cs0_4 e1uc[5] siul dspi_3 dspi_4 emios_1 i/o o i/o i/o m tristate ? ? 140 a14 ph[12] pcr[124] af0 af1 af2 af3 gpio[124] sck_3 cs1_4 e1uc[25] siul dspi_3 dspi_4 emios_1 i/o i/o o i/o m tristate ? ? 141 d12 ph[13] pcr[125] af0 af1 af2 af3 gpio[125] sout_4 cs0_3 e1uc[26] siul dspi_4 dspi_3 emios_1 i/o o i/o i/o mtristate ? ? 9 b3 ph[14] pcr[126] af0 af1 af2 af3 gpio[126] sck_4 cs1_3 e1uc[27] siul dspi_4 dspi_3 emios_1 i/o i/o o i/o m tristate ? ? 10 d1 ph[15] pcr[127] af0 af1 af2 af3 gpio[127] sout_5 ? e1uc[17] siul dspi_5 ? emios_1 i/o o ? i/o mtristate ? ? 8 a3 port i table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
spc560b54x/6x package pinouts and signal descriptions docid15131 rev 9 49/133 pi[0] pcr[128] af0 af1 af2 af3 gpio[128] e0uc[28] lin8tx ? siul emios_0 linflex_8 ? i/o i/o o ? s tristate ? ? 172 a9 pi[1] pcr[129] af0 af1 af2 af3 ? ? gpio[129] e0uc[29] ? ? wkpu[24] (5) lin8rx siul emios_0 ? ? wkpu linflex_8 i/o i/o ? ? i i s tristate ? ? 171 a10 pi[2] pcr[130] af0 af1 af2 af3 gpio[130] e0uc[30] lin9tx ? siul emios_0 linflex_9 ? i/o i/o o ? s tristate ? ? 170 b10 pi[3] pcr[131] af0 af1 af2 af3 ? ? gpio[131] e0uc[31] ? ? wkpu[23] (5) lin9rx siul emios_0 ? ? wkpu linflex_9 i/o i/o ? ? i i s tristate ? ? 169 c10 pi[4] pcr[132] af0 af1 af2 af3 gpio[132] e1uc[28] sout_4 ? siul emios_1 dspi_4 ? i/o i/o o ? s tristate ? ? 143 a12 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
package pinouts and signal descriptions spc560b54x/6x 50/133 docid15131 rev 9 pi[5] pcr[133] af0 af1 af2 af3 gpio[133] e1uc[29] sck_4 ? siul emios_1 dspi_4 ? i/o i/o i/o ? s tristate ? ? 142 c12 pi[6] pcr[134] af0 af1 af2 af3 gpio[134] e1uc[30] cs0_4 ? siul emios_1 dspi_4 ? i/o i/o i/o ? s tristate ? ? 11 d2 pi[7] pcr[135] af0 af1 af2 af3 gpio[135] e1uc[31] cs1_4 ? siul emios_1 dspi_4 ? i/o i/o o ? s tristate ? ? 12 d3 pi[8] pcr[136] af0 af1 af2 af3 ? gpio[136] ? ? ? adc0_s[16] siul ? ? ? adc_0 i/o ? ? ? i j tristate ? ? 108 j13 pi[9] pcr[137] af0 af1 af2 af3 ? gpio[137] ? ? ? adc0_s[17] siul ? ? ? adc_0 i/o ? ? ? i j tristate ? ? 109 j14 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
spc560b54x/6x package pinouts and signal descriptions docid15131 rev 9 51/133 pi[10] pcr[138] af0 af1 af2 af3 ? gpio[138] ? ? ? adc0_s[18] siul ? ? ? adc_0 i/o ? ? ? i j tristate ? ? 110 j15 pi[11] pcr[139] af0 af1 af2 af3 ? ? gpio[139] ? ? ? adc0_s[19] sin_3 siul ? ? ? adc_0 dspi_3 i/o ? ? ? i i j tristate ? ? 111 j16 pi[12] pcr[140] af0 af1 af2 af3 ? gpio[140] cs0_3 ? ? adc0_s[20] siul dspi_3 ? ? adc_0 i/o i/o ? ? i j tristate ? ? 112 g14 pi[13] pcr[141] af0 af1 af2 af3 ? gpio[141] cs1_3 ? ? adc0_s[21] siul dspi_3 ? ? adc_0 i/o o ? ? i j tristate ? ? 113 g15 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
package pinouts and signal descriptions spc560b54x/6x 52/133 docid15131 rev 9 pi[14] pcr[142] af0 af1 af2 af3 ? ? gpio[142] ? ? ? adc0_s[22] sin_4 siul ? ? ? adc_0 dspi_4 i/o ? ? ? i i j tristate ? ? 76 r8 pi[15] pcr[143] af0 af1 af2 af3 ? gpio[143] cs0_4 ? ? adc0_s[23] siul dspi_4 ? ? adc_0 i/o i/o ? ? i j tristate ? ? 75 t8 port j pj[0] pcr[144] af0 af1 af2 af3 ? gpio[144] cs1_4 ? ? adc0_s[24] siul dspi_4 ? ? adc_0 i/o o ? ? i j tristate ? ? 74 n5 pj[1] pcr[145] af0 af1 af2 af3 ? ? gpio[145] ? ? ? adc0_s[25] sin_5 siul ? ? ?? adc_0 dspi_5 i/o ? ? ? i i j tristate ? ? 73 p5 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
spc560b54x/6x package pinouts and signal descriptions docid15131 rev 9 53/133 pj[2] pcr[146] af0 af1 af2 af3 ? gpio[146] cs0_5 ? ? adc0_s[26] siul dspi_5 ? ? adc_0 i/o i/o ? ? i j tristate ? ? 72 p4 pj[3] pcr[147] af0 af1 af2 af3 ? gpio[147] cs1_5 ? ? adc0_s[27] siul dspi_5 ? ? adc_0 i/o o ? ? i j tristate ? ? 71 p2 pj[4] pcr[148] af0 af1 af2 af3 gpio[148] sck_5 e1uc[18] ? siul dspi_5 emios_1 ? i/o i/o i/o ? mtristate ? ? 5 a4 1. alternate functions are chosen by se tting the values of the pcr.pa bitfields inside the siul module. pcr.pa = 00 ? af0; pcr.pa = 01 ? af1; pcr.pa = 10 ? af2; pcr.pa = 11 ? af2. this is intended to select the output functions; to use one of the input functions, the pcr.ibe bit must be written to ?1 ?, regardless of the values selected in the pcr.pa bitfields. for this reason, the val ue corresponding to an input only function is reported as ???. 2. multiple inputs are routed to all respective modules internally . the input of some modules must be configured by setting the values of the psmio.padselx bitfields inside the siul module. 3. the reset configuration applies during and after reset. 4. lbga208 available only as dev elopment package for nexus2+ 5. all wkpu pins also support external interrupt ca pability. see the wkpu chapter for further details. 6. nmi has higher priority than alternate function. when nmi is selected, the pcr.af field is ignored. 7. ?not applicable? because these functions ar e available only while the device is booting. refer to the bam information for det ails. 8. value of pcr.ibe bit must be 0. 9. this wakeup input cannot be used to exit standby mode. table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration (3) pin number lqfp 100 lqfp 144 lqfp 176 lbga 208 (4)
package pinouts and signal descriptions spc560b54x/6x 54/133 docid15131 rev 9 10. out of reset all the functional pins except pc[0:1 ] and ph[9:10] are available to the user as gpio. ? pc[0:1] are available as jtag pins (tdi and tdo respectively). ? ph[9:10] are available as jtag pins (tck and tms respectively). ? it is up to the user to configure these pins as gpio when needed. 11. pc[1] is a fast/medium pad but is in medium configuration by default. this pad is in alter nate function 2 mode after reset w hich has tdo functionality. the reset value of pcr.obe is ?1?, but this setting has no impa ct as long as this pad stays in af2 mode. after configuring this pad as gpio (pcr.p a = 0), output buffer is enabled as reset value of pcr.obe = 1. 12. not available in lqfp100 package.
docid15131 rev 9 55/133 spc560b54x/6x package pinouts and signal descriptions 132 3.8 nexus 2+ pins in the lbga208 package, eight addition al debug pins are available (see table 7 ). table 7. nexus 2+ pin descriptions port pin function i/o direction pad type function after reset pin number lqfp 100 lqfp 144 lbga 208 (1) mcko message clock out o f ? ? ? t4 mdo0 message data out 0 o m ? ? ? h15 mdo1 message data out 1 o m ? ? ? h16 mdo2 message data out 2 o m ? ? ? h14 mdo3 message data out 3 o m ? ? ? h13 evti event in i m pull-up ? ? k1 evto event out o m ? ? ? l4 mseo message start/end out o m ? ? ? g16 1. lbga208 available only as development package for nexus2+.
electrical characteri stics spc560b54x/6x 56/133 docid15131 rev 9 4 electrical characteristics this section contains electrical characterist ics of the device as well as temperature and power considerations. this product contains devices to protect the inputs against damage due to high static voltages. however, it is advisable to take precautions to avoid application of any voltage higher than the specified maximum rated voltages. to enhance reliability, unused i nputs can be driven to an appropriate logic voltage level (v dd or v ss ). this could be done by the internal pull- up and pull-down, which is provided by the product for most general purpose pins. the parameters listed in the following tables r epresent the characteristics of the device and its demands on the system. in the tables where the device logic prov ides signals with their respective timing characteristics, the symbol ?cc? for controller characteristics is included in the symbol column. in the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol ?sr? for system requirement is included in the symbol column. 4.1 parameter classification the electrical parameters shown in this su pplement are guaranteed by various methods. to give the customer a better understanding, the classifications listed in table 8 are used and the parameters are tagged accordingly in the tables where appropriate. note: the classification is s hown in the column labeled ?c? in the parameter tables where appropriate. 4.2 nvusro register bit values in the non-volatile user options (nvusro) register control portions of the device configuration, namely electrical parameters such as high voltage supply and oscillator margin, as well as digital functio nality (watchdog enable/disable after reset). table 8. paramete r classifications classification tag tag description p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design characterization by measuring a statistically relevant sample size ac ross process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless othe rwise noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations.
docid15131 rev 9 57/133 spc560b54x/6x electrical characteristics 132 for a detailed description of the nvusro regi ster, please refer to the device reference manual. 4.2.1 nvusro[pad3v5v ] field description the dc electrical characteristics are dependent on the pad3v5v bit value. table 9 shows how nvusro[pad3v5v] controls the device configuration. 4.2.2 nvusro[oscillator_margin] field description the fast external cryst al oscillator consumptio n is dependent on the oscillator_margin bit value. table 10 shows how nvusro[oscillator_margin] controls the device configuration. 4.2.3 nvusro[watchdog_ en] field description the watchdog enable/disable configuration after reset is dependent on the watchdog_en bit value. table 11 shows how nvusro[watc hdog_en] controls the device configuration. table 9. pad3v5v field description (1) 1. see the device reference manual for more information on the nvusro register. value (2) 2. default manufacturing value is ?1?. value can be programmed by customer in shadow flash. description 0 high voltage supply is 5.0 v 1 high voltage supply is 3.3 v table 10. oscillator_margin field description (1) 1. see the device reference manual for more information on the nvusro register. value (2) 2. default manufacturing value is ?1?. value can be programmed by customer in shadow flash. description 0 low consumption configuration (4 mhz/8 mhz) 1 high margin configuration (4 mhz/16 mhz) table 11. watchdog_en field description value (1) 1. default manufacturing value is ?1?. value can be programmed by customer in shadow flash. description 0 disable after reset 1 enable after reset
electrical characteri stics spc560b54x/6x 58/133 docid15131 rev 9 4.3 absolute maximum ratings note: stresses exceeding the recommended absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly and functional operati on of the device at these or any other conditions above those indi cated in the operational sections of this specification are not implied. exposure to abso lute maximum rating conditions for extended periods may affect device reliabilit y. during overload conditions (v in > v dd or v in < v ss ), the voltage on pins with respect to ground (v ss ) must not exceed the recommended values. table 12. absolute maximum ratings symbol parameter conditions value unit min max v ss sr digital ground on vss_hv pins ? 0 0 v v dd sr voltage on vdd_hv pins with respect to ground (v ss ) ??0.36.0v v ss_lv sr voltage on vss_lv (low voltage digital supply) pins with respect to ground (v ss ) ?v ss ? 0.1 v ss + 0.1 v v dd_bv sr voltage on vdd_bv (regulator supply) pin with respect to ground (v ss ) ??0.36.0 v relative to v dd ?0.3 v dd + 0.3 v ss_adc sr voltage on vss_hv_adc0, vss_hv_adc1 (adc reference) pins with respect to ground (v ss ) ?v ss ? 0.1 v ss + 0.1 v v dd_adc sr voltage on vdd_hv_adc0, vdd_hv_adc1 (adc reference) pins with respect to ground (v ss ) ??0.36.0 v relative to v dd v dd ??? 0.3 v dd + 0.3 v in sr voltage on any gpio pin with respect to ground (v ss ) ??0.36.0 v relative to v dd ?v dd + 0.3 i injpad sr injected input current on any pin during overload condition ??1010 ma i injsum sr absolute sum of all injected input currents during overload condition ??5050 i avgseg sr sum of all the static i/o current within a supply segment v dd = 5.0 v 10%, pad3v5v = 0 ?70 ma v dd = 3.3 v 10%, pad3v5v = 1 ?64 t storage sr storage temperature ? ?55 150 c
docid15131 rev 9 59/133 spc560b54x/6x electrical characteristics 132 4.4 recommended operating conditions table 13. recommended operating conditions (3.3 v) symbol parameter conditions value unit min max v ss sr digital ground on vss_hv pins ? 0 0 v v dd (1) sr voltage on vdd_hv pins with respect to ground (v ss ) ?3.03.6v v ss_lv (2) sr voltage on vss_lv (low voltage digital supply) pins with respect to ground (v ss ) ?v ss ?? 0.1 v ss + 0.1 v v dd_bv (3) sr voltage on vdd_bv pin (regulator supply) with respect to ground (v ss ) ?3.03.6 v relative to v dd v dd ?? 0.1 v dd + 0.1 v ss_adc sr voltage on vss_hv_adc0, vss_hv_adc1 (adc re ference) pin with respect to ground (v ss ) ?v ss ?? 0.1 v ss + 0.1 v v dd_adc (4) sr voltage on vdd_hv_adc0, vdd_hv_adc1 (adc reference) with respect to ground (v ss ) ?3.0 (5) 3.6 v relative to v dd v dd ?? 0.1 v dd + 0.1 v in sr voltage on any gpio pin with respect to ground (v ss ) ?v ss ?? 0.1 ? v relative to v dd ?v dd + 0.1 i injpad sr injected input current on any pin during overload condition ? ? 55 ma i injsum sr absolute sum of all injected input currents during overload condition ? ? 50 50 tv dd sr v dd slope to ensure correct power up (6) ?3.0 (7) 250 x 10 3 (0.25 [v/s]) v/s 1. 100 nf capacitance needs to be provided between each v dd /v ss pair. 2. 330 nf capacitance needs to be provided between each v dd_lv /v ss_lv supply pair. 3. 470 nf capacitance needs to be provided between v dd_bv and the nearest v ss_lv (higher value may be needed depending on external regulator characteri stics). supply ramp slope on vdd_bv shoul d always be faster or equal to slope of vdd_hv. otherwise, device may enter regulator bypass mode if slope on vdd_bv is slower. 4. 100 nf capacitance needs to be provided between v dd_adc /v ss_adc pair. 5. full electrical specific ation cannot be guaranteed when voltage drops belo w 3.0 v. in particular, adc electrical characteristics and i/os dc electric al specification may not be guaranteed. when voltage drops below v lvdhvl , device is reset. 6. guaranteed by device validation. 7. minimum value of tv dd must be guaranteed until v dd reaches 2.6 v (maximum value of v porh ).
electrical characteri stics spc560b54x/6x 60/133 docid15131 rev 9 note: ram data retention is guaranteed with v dd_lv not below 1.08 v. table 14. recommended operating conditions (5.0 v) symbol parameter conditions value unit min max v ss s r digital ground on vss_hv pins ? 0 0 v v dd (1) s r voltage on vdd_hv pins with respect to ground (v ss ) ?4.55.5 v voltage drop (2) 3.0 5.5 v ss_lv (3) s r voltage on vss_lv (low voltage digital supply) pins with respect to ground (v ss ) ?v ss ? 0.1 v ss + 0.1 v v dd_bv (4) s r voltage on vdd_bv pin (regulator supply) with respect to ground (v ss ) ?4.55.5 v voltage drop (2) 3.0 5.5 relative to v dd 3.0 v dd + 0.1 v ss_adc s r voltage on vss_hv_adc0, vss_hv_adc1 (adc reference) pin with respect to ground (v ss ) ?v ss ? 0.1 v ss + 0.1 v v dd_adc (5) s r voltage on vdd_hv_adc0, vdd_hv_adc1 (adc reference) with respect to ground (v ss ) ?4.55.5 v voltage drop (2) 3.0 5.5 relative to v dd v dd ? 0.1 v dd + 0.1 v in s r voltage on any gpio pin with respect to ground (v ss ) ?v ss ? 0.1 ? v relative to v dd ?v dd + 0.1 i injpad s r injected input current on any pin during overload condition ? ? 55 ma i injsum s r absolute sum of all injected input currents during overload condition ? ? 50 50 tv dd s r v dd slope to ensure correct power up (6) ?3.0 (7) 250 x 10 3 (0.25 [v/s]) v/s 1. 100 nf capacitance needs to be provided between each v dd /v ss pair. 2. full device operation is guaranteed by des ign when the voltage drops below 4.5 v down to 3.0 v. however, certain analog electrical characteri stics will not be guaranteed to stay within the stated limits. 3. 330 nf capacitance needs to be provided between each v dd_lv /v ss_lv supply pair. 4. 470 nf capacitance needs to be provided between v dd_bv and the nearest v ss_lv (higher value may be needed depending on external regulator characteristics). while the supply voltage ramps up, the slope on v dd_bv should be less than 0.9v dd_hv in order to ensure the device does not enter regulator bypass mode. 5. 100 nf capacitance needs to be provided between v dd_adc /v ss_adc pair. 6. guaranteed by device validation. 7. minimum value of tv dd must be guaranteed until v dd reaches 2.6 v (maximum value of v porh ).
docid15131 rev 9 61/133 spc560b54x/6x electrical characteristics 132 4.5 thermal characteristics 4.5.1 external ballast resistor recommendations external ballast resistor on v dd_bv pin helps in reducing the overall power dissipation inside the device. this resist or is required only when maximum power consumption exceeds the limit imposed by package thermal characteristics. as stated in table 15 lqfp thermal characteristics, co nsidering a thermal resistance of lqfp144 as 48.3 c/w, at ambient temperature t a = 125 c, the junction temperature t j will cross 150 c if the total power dissipation is greater than (150 ? 125)/48.3 = 517 mw. therefore, the total device current i ddmax at 125 c/5.5 v must not exceed 94.1 ma (i.e., pd/vdd). assuming an average i dd (v dd_hv ) of 15?20 ma consumption typically during device run mode, the lv domain consumption i dd (v dd_bv ) is thus limited to i ddmax ? i dd (v dd_hv ), i.e., 80 ma. therefore, respecting the maximu m power allowed as explained in section 4.5.2: package thermal characteristics , it is recommended to use this resistor only in the 125 c/5.5 v operating corner as per the following guidelines: ? if i dd (v dd_bv ) < 80 ma, then no resistor is required. ? if 80 ma < i dd (v dd_bv ) < 90 ma, then 4 ? resistor can be used. ? if i dd (v dd_bv ) > 90 ma, then 8 ? resistor can be used. using resistance in the range of 4?8 ? , the gain will be around 10? 20% of total consumption on v dd_bv . for example, if 8 ? resistor is used, then power consumption when i dd (v dd_bv ) is 110 ma is equivalent to power consumption when i dd (v dd_bv ) is 90 ma (approximately) when resistor not used. in order to ensure correct power up, the minimum v dd_bv to be guaranteed is 30 ms/v. if the supply ramp is slower than this value, then lvdhv3 b monitoring ballast supply v dd_bv pin gets triggered leading to device reset. until the supply reaches certain threshold, this low voltage detector (lvd) generates destructive reset event in the system. this threshold depends on the maximum i dd (v dd_bv ) possible across the external resistor. 4.5.2 package thermal characteristics table 15. lqfp thermal characteristics (1) symbol c parameter conditions (2) pin count value unit min typ max r ? ja cc d thermal resistance, junction-to- ambient natural convection (3) single-layer board ? 1s 100 ? ? 64 c/w 144 ? ? 64 176 ? ? 64 four-layer board ? 2s2p 100 ? ? 49.7 144 ? ? 48.3 176 ? ? 47.3
electrical characteri stics spc560b54x/6x 62/133 docid15131 rev 9 4.5.3 power considerations the average chip-junction temperature, t j , in degrees celsius, may be calculated using equation 1 : equation 1 t j = t a + (p d x r ? ja ) where: t a is the ambient temperature in c. r ? ja is the package junction-to-ambient thermal resistance, in c/w. p d is the sum of p int and p i/o (p d = p int + p i/o ). p int is the product of i dd and v dd , expressed in watts. this is the chip internal power. p i/o represents the power dissipation on input and output pins; user determined. most of the time for the applications, p i/o < p int and may be neglected. on the other hand, p i/o may be significant, if the device is confi gured to continuously drive external modules and/or memories. an approximate relationship between p d and t j (if p i/o is neglected) is given by: r ? jb cc thermal resistance, junction-to- board (4) single-layer board ? 1s 100 ? ? 36 c/w 144 ? ? 38 176 ? ? 38 four-layer board ? 2s2p 100 ? ? 33.6 144 ? ? 33.4 176 ? ? 33.4 r ? jc cc thermal resistance, junction-to- case (5) single-layer board ? 1s 100 ? ? 23 c/w 144 ? ? 23 176 ? ? 23 four-layer board ? 2s2p 100 ? ? 19.8 144 ? ? 19.2 176 ? ? 18.8 1. thermal characteristics are targets based on simulation. 2. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c. 3. junction-to-ambient thermal resistance determined per jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. when greek lette rs are not available, the symbols are typed as r thja and r thjma . 4. junction-to-board thermal resistance determined per jedec jesd51-8. thermal te st board meets jedec specification for the specified package. when greek letters are not available, the symbols are typed as r thjb . 5. junction-to-case at the top of the package determined usi ng mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported value includes the t hermal resistance of the interface layer. when greek letters are not available, the symbols are typed as r thjc . table 15. lqfp thermal characteristics (1) (continued) symbol c parameter conditions (2) pin count value unit min typ max
docid15131 rev 9 63/133 spc560b54x/6x electrical characteristics 132 equation 2 p d = k / (t j + 273 c) therefore, solving equations 1 and 2 : equation 3 k = p d x (t a + 273 c) + r ? ja x p d 2 where: k is a constant for the particular part, which may be determined from equation 3 by measuring p d (at equilibrium) for a known t a. using this value of k, the values of p d and t j may be obtained by solving equations equation 1 and equation 2 iteratively for any value of t a . 4.6 i/o pad electric al characteristics 4.6.1 i/o pad types the device provides four main i/o pad types depending on the associated alternate functions: ? slow pads?are the most common pads, providing a good compromise between transition time and low electromagnetic emission. ? medium pads?provide transition fast enou gh for the serial communication channels with controlled current to reduce electromagnetic emission. ? fast pads?provide maximum speed. these are used for improved nexus debugging capability. ? input only pads?are associated with ad c channels and 32 khz low power external crystal oscillator providing low input leakage. medium and fast pads can use slow configurat ion to reduce electromagnetic emission, at the cost of reducing ac performance. 4.6.2 i/o input dc characteristics table 16 provides input dc electrical characteristics as described in figure 6 .
electrical characteri stics spc560b54x/6x 64/133 docid15131 rev 9 figure 6. i/o input dc electrical characteristics definition v il v in v ih pdix = ?1 v dd v hys (gpdi register of siul) pdix = ?0? table 16. i/o input dc electrical characteristics symbol c parameter conditions (1) value unit min typ max v ih sr p input high level cmos (schmitt trigger) ?0.65v dd ?v dd + 0.4 v v il sr p input low level cmos (schmitt trigger) ? ? 0.4 ? 0.35v dd v hys cc c input hysteresis cmos (schmitt trigger) ?0.1v dd ?? i lkg cc d digital input leakage no injection on adjacent pin t a = ? 40 c ? 2 200 na dt a = 25 c ? 2 200 dt a = 85 c ? 5 300 dt a = 105 c ? 12 500 pt a = 125 c ? 70 1000 w fi (2) sr p wakeup input filtered pulse ? ? ? 40 ns w nfi (2 ) sr p wakeup input not filtered pulse ? 1000 ? ? ns 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. in the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and voltage.
docid15131 rev 9 65/133 spc560b54x/6x electrical characteristics 132 4.6.3 i/o output dc characteristics the following tables provide dc characteristics for bidirectional pads: ? table 17 provides weak pull figures. both pull-up and pull-down resistances are supported. ? table 18 provides output driver characte ristics for i/o pads when in slow configuration. ? table 19 provides output driver characteri stics for i/o pads when in medium configuration. ? table 20 provides output driver characte ristics for i/o pads when in fast configuration. table 17. i/o pull-up/pull-down dc electrical characteristics symbol c parameter conditions (1) value unit min typ max |i wpu |cc p weak pull-up current absolute value v in = v il , v dd = 5.0 v 10% pad3v5v = 0 10 ? 150 a c pad3v5v = 1 (2) 10 ? 250 pv in = v il , v dd = 3.3 v 10% pad3v5v = 1 10 ? 150 |i wpd |cc p weak pull-down current absolute value v in = v ih , v dd = 5.0 v 10% pad3v5v = 0 10 ? 150 a c pad3v5v = 1 10 ? 250 pv in = v ih , v dd = 3.3 v 10% pad3v5v = 1 10 ? 150 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. the configuration pad3v5 = 1 when v dd = 5 v is only a transient configurati on during power-up. all pads but reset and nexus output (mdox, evto, mcko) are configured in input or in high impedance state. table 18. slow configuration output buffer electrical characteristics symbol c parameter conditions (1) value unit min typ max v oh c c p output high level ? slow configuration push pull i oh = ? 2 ma, ? v dd = 5.0 v 10%, pad3v5v = 0 ? (recommended) 0.8v dd ?? v c i oh = ? 2 ma, ? v dd = 5.0 v 10%, pad3v5v = 1 (2) 0.8v dd ?? c i oh = ? 1 ma, ? v dd = 3.3 v 10%, pad3v5v = 1 ? (recommended) v dd ??? 0.8 ? ?
electrical characteri stics spc560b54x/6x 66/133 docid15131 rev 9 v ol c c p output low level ? slow configuration push pull i ol = 2 ma, ? v dd = 5.0 v 10%, pad3v5v = 0 ? (recommended) ? ? 0.1v dd v c i ol = 2 ma, ? v dd = 5.0 v 10%, pad3v5v = 1 (2) ? ? 0.1v dd c i ol = 1 ma, ? v dd = 3.3 v 10%, pad3v5v = 1 ? (recommended) ??0.5 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. the configuration pad3v5 = 1 when v dd = 5 v is only a transient configurati on during power-up. all pads but reset and nexus output (mdox, evto, mcko) are configured in input or in high impedance state. table 18. slow configuration output buffer electrical characteristics (continued) symbol c parameter conditions (1) value unit min typ max table 19. medium configuration output buffer electrical characteristics symbol c parameter conditions (1) value unit min typ max v oh cc c output high level ? medium configuration push pull i oh = ? 3.8 ma, ? v dd = 5.0 v 10%, pad3v5v = 0 0.8v dd ?? v p i oh = ? 2 ma, ? v dd = 5.0 v 10%, pad3v5v = 0 ? (recommended) 0.8v dd ?? c i oh = ? 1 ma, ? v dd = 5.0 v 10%, pad3v5v = 1 (2) 0.8v dd ?? c i oh = ? 1 ma, ? v dd = 3.3 v 10%, pad3v5v = 1 ? (recommended) v dd ?? 0.8 ? ? c i oh = ? 100 a, ? v dd = 5.0 v 10%, pad3v5v = 0 0.8v dd ?? v ol cc c output low level ? medium configuration push pull i ol = 3.8 ma, ? v dd = 5.0 v 10%, pad3v5v = 0 ??0.2v dd v p i ol = 2 ma, ? v dd = 5.0 v 10%, pad3v5v = 0 ? (recommended) ??0.1v dd c i ol = 1 ma, ? v dd = 5.0 v 10%, pad3v5v = 1 (2) ??0.1v dd c i ol = 1 ma, ? v dd = 3.3 v 10%, pad3v5v = 1 ? (recommended) ??0.5 c i ol = 100 a, ? v dd = 5.0 v 10%, pad3v5v = 0 ??0.1v dd
docid15131 rev 9 67/133 spc560b54x/6x electrical characteristics 132 4.6.4 output pin transition times 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. the configuration pad3v5 = 1 when v dd = 5 v is only a transient configuration during power-up. all pads but reset and nexus output (mdox, evto, mcko) are configured in input or in high impedance state. table 20. fast configuration output buffer electrical characteristics symbol c parameter conditions (1) value unit min typ max v oh c c p output high level ? fast configuration push pull i oh = ? 14 ma, ? v dd = 5.0 v 10%, pad3v5v = 0 ? (recommended) 0.8v dd ?? v c i oh = ? 7 ma, ? v dd = 5.0 v 10%, pad3v5v = 1 (2) 0.8v dd ?? c i oh = ? 11 ma, ? v dd = 3.3 v 10%, pad3v5v = 1 (recommended) v dd ? ? 0.8 ?? v ol c c p output low level ? fast configuration push pull i ol = 14 ma, ? v dd = 5.0 v 10%, pad3v5v = 0 ? (recommended) ? ? 0.1v dd v c i ol = 7 ma, ? v dd = 5.0 v 10%, pad3v5v = 1 (2) ? ? 0.1v dd c i ol = 11 ma, ? v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. the configuration pad3v5 = 1 when v dd = 5 v is only a transient configurati on during power-up. all pads but reset and nexus output (mdox, evto, mcko) are configured in input or in high impedance state. table 21. output pin transition times symbol c parameter conditions (1) value unit min typ max t tr cc d output transition time output pin (2) ? slow configuration c l = 25 pf v dd = 5.0 v 10%, ? pad3v5v = 0 ??50 ns tc l = 50 pf ? ? 100 dc l = 100 pf ? ? 125 dc l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 ??50 tc l = 50 pf ? ? 100 dc l = 100 pf ? ? 125
electrical characteri stics spc560b54x/6x 68/133 docid15131 rev 9 4.6.5 i/o pad current specification the i/o pads are distributed across the i/o su pply segment. each i/o supply segment is associated to a v dd /v ss supply pair as described in table 22 . table 23 provides i/o consumption figures. in order to ensure device reliability, the aver age current of the i/o on a single segment should remain below the i avgseg maximum value. t tr cc d output transition time output pin (2) ? medium configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 siul.pcrx.src = 1 ??10 ns tc l = 50 pf ? ? 20 dc l = 100 pf ? ? 40 dc l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 siul.pcrx.src = 1 ??12 tc l = 50 pf ? ? 25 dc l = 100 pf ? ? 40 t tr cc d output transition time output pin (2) ? fast configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ?? 4 ns c l = 50 pf ? ? 6 c l = 100 pf ? ? 12 c l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 ?? 4 c l = 50 pf ? ? 7 c l = 100 pf ? ? 12 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. c l includes device and package capacitances (c pkg < 5 pf). table 21. output pin transition times (continued) symbol c parameter conditions (1) value unit min typ max table 22. i/o supply segments package supply segment 12345678 lbga208 (1) equivalent to lqfp176 segment pad distribution mcko mdon /mseo lqfp176 pin7 ? pin27 pin28 ? pin57 pin59 ? pin85 pin86 ? pin123 pin124 ? pin150 pin151 ? pin6 ? ? lqfp144 pin20 ? pin49 pin51 ? pin99 pin100 ? pin122 pin 123 ? pin19 ? ? ? ? lqfp100 pin16 ? pin35 pin37 ? pin69 pin70 ? pin83 pin84 ? pin15 ? ? ? ? 1. lbga208 available only as development package for nexus2+.
docid15131 rev 9 69/133 spc560b54x/6x electrical characteristics 132 table 24 provides the weight of concurrent switching i/os. table 23. i/o consumption symbol c parameter conditions (1) value unit min typ max i swtslw (2) cc d dynamic i/o current for slow configuration c l = 25 pf v dd = 5.0 v 10%, ? pad3v5v = 0 ??20 ma v dd = 3.3 v 10%, ? pad3v5v = 1 ??16 i swtmed (2) cc d dynamic i/o current for medium configuration c l = 25 pf v dd = 5.0 v 10%, ? pad3v5v = 0 ??29 ma v dd = 3.3 v 10%, ? pad3v5v = 1 ??17 i swtfst (2) cc d dynamic i/o current for fast configuration c l = 25 pf v dd = 5.0 v 10%, ? pad3v5v = 0 ??110 ma v dd = 3.3 v 10%, ? pad3v5v = 1 ??50 i rmsslw cc d root mean square i/o current for slow configuration c l = 25 pf, 2 mhz v dd = 5.0 v 10%, ? pad3v5v = 0 ??2.3 ma c l = 25 pf, 4 mhz ? ? 3.2 c l = 100 pf, 2 mhz ? ? 6.6 c l = 25 pf, 2 mhz v dd = 3.3 v 10%, ? pad3v5v = 1 ??1.6 c l = 25 pf, 4 mhz ? ? 2.3 c l = 100 pf, 2 mhz ? ? 4.7 i rmsmed cc d root mean square i/o current for medium configuration c l = 25 pf, 13 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??6.6 ma c l = 25 pf, 40 mhz ? ? 13.4 c l = 100 pf, 13 mhz ? ? 18.3 c l = 25 pf, 13 mhz v dd = 3.3 v 10%, pad3v5v = 1 ?? 5 c l = 25 pf, 40 mhz ? ? 8.5 c l = 100 pf, 13 mhz ? ? 11 i rmsfst cc d root mean square i/o current for fast configuration c l = 25 pf, 40 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??22 ma c l = 25 pf, 64 mhz ? ? 33 c l = 100 pf, 40 mhz ? ? 56 c l = 25 pf, 40 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??14 c l = 25 pf, 64 mhz ? ? 20 c l = 100 pf, 40 mhz ? ? 35 i avgseg sr d sum of all the static i/o current within a supply segment v dd = 5.0 v 10%, pad3v5v = 0 ? ? 70 ma v dd = 3.3 v 10%, pad3v5v = 1 ? ? 65 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to125 c, unless otherwise specified 2. stated maximum values represent peak consumpti on that lasts only a few ns during i/o transition.
electrical characteri stics spc560b54x/6x 70/133 docid15131 rev 9 due to the dynamic current limitations, the sum of the weight of concur rent switching i/os on a single segment must not exceed 1 00% to ensure device functionality. table 24. i/o weight (1) supply segment pad lqfp176 lqfp144/100 weight 5 v weight 3.3 v weight 5 v weight 3.3 v lqfp 176 lqfp 144 lqfp 100 src (2) = 0 src = 1 src = 0 src = 1 src = 0 src = 1 src = 0 src = 1 6 44 pb[3] 5% ? 6% ? 13% ? 15% ? pc[9] 4% ? 5% ? 13% ? 15% ? pc[14] 4% ? 4% ? 13% ? 15% ? pc[15] 3% 4% 4% 4% 12% 18% 15% 16% ??pj[4]3%4%3%3%???? 1 ??ph[15]2%3%3%3%???? ??ph[13]3%4%3%4%???? ??ph[14]3%4%4%4%???? ??pi[6]4%?4%????? ??pi[7]4%?4%????? 4 ? pg[5] 4% ? 5% ? 10% ? 12% ? ? pg[4] 4% 6% 5% 5% 9% 13% 11% 12% ? pg[3] 4% ? 5% ? 9% ? 11% ? ? pg[2] 4% 6% 5% 5% 9% 12% 10% 11% 4 pa[2] 4% ? 5% ? 8% ? 10% ? pe[0] 4% ? 5% ? 8% ? 9% ? pa[1] 4% ? 5% ? 8% ? 9% ? pe[1] 4% 6% 5% 6% 7% 10% 9% 9% pe[8] 4% 6% 5% 6% 7% 10% 8% 9% pe[9] 4% ? 5% ? 6% ? 8% ? pe[10] 4% ? 5% ? 6% ? 7% ? pa[0]4% 6%5%5%6%8%7%7% pe[11] 4% ? 5% ? 5% ? 6% ?
docid15131 rev 9 71/133 spc560b54x/6x electrical characteristics 132 21 ? pg[9] 9% ? 10% ? 9% ? 10% ? ? pg[8] 9% ? 11% ? 9% ? 11% ? 1 pc[11] 9% ? 11% ? 9% ? 11% ? pc[10] 9% 13% 11% 12% 9% 13% 11% 12% ? pg[7] 9% ? 11% ? 9% ? 11% ? ? pg[6] 10% 14% 11% 12% 10% 14% 11% 12% 1 pb[0] 10% 14% 12% 12% 10% 14% 12% 12% pb[1] 10% ? 12% ? 10% ? 12% ? ? pf[9] 10% ? 12% ? 10% ? 12% ? ? pf[8] 10% 14% 12% 13% 10% 14% 12% 13% ? pf[12] 10% 15% 12% 13% 10% 15% 12% 13% 1 pc[6] 10% ? 12% ? 10% ? 12% ? pc[7] 10% ? 12% ? 10% ? 12% ? ? pf[10] 10% 14% 11% 12% 10% 14% 11% 12% ? pf[11] 9% ? 11% ? 9% ? 11% ? 1 pa[15] 8% 12% 10% 10% 8% 12% 10% 10% ? pf[13] 8% ? 10% ? 8% ? 10% ? 1 pa[14] 8% 11% 9% 10% 8% 11% 9% 10% pa[4] 7% ? 9% ? 7% ? 9% ? pa[13] 7% 10% 8% 9% 7% 10% 8% 9% pa[12] 7% ? 8% ? 7% ? 8% ? table 24. i/o weight (1) (continued) supply segment pad lqfp176 lqfp144/100 weight 5 v weight 3.3 v weight 5 v weight 3.3 v lqfp 176 lqfp 144 lqfp 100 src (2) = 0 src = 1 src = 0 src = 1 src = 0 src = 1 src = 0 src = 1
electrical characteri stics spc560b54x/6x 72/133 docid15131 rev 9 3 2 2 pb[9] 1% ? 1% ? 1% ? 1% ? pb[8] 1% ? 1% ? 1% ? 1% ? pb[10] 5% ? 6% ? 6% ? 7% ? ? pf[0] 5% ? 6% ? 6% ? 8% ? ? pf[1] 5% ? 6% ? 7% ? 8% ? ? pf[2] 6% ? 7% ? 7% ? 9% ? ? pf[3] 6% ? 7% ? 8% ? 9% ? ? pf[4] 6% ? 7% ? 8% ? 10% ? ? pf[5] 6% ? 7% ? 9% ? 10% ? ? pf[6] 6% ? 7% ? 9% ? 11% ? ? pf[7] 6% ? 7% ? 9% ? 11% ? ??pj[3]6%?7%????? ??pj[2]6%?7%????? ??pj[1]6%?7%????? ??pj[0]6%?7%????? ??pi[15]6%?7%????? ??pi[14]6%?7%????? 22 pd[0] 1% ? 1% ? 1% ? 1% ? pd[1] 1% ? 1% ? 1% ? 1% ? pd[2] 1% ? 1% ? 1% ? 1% ? pd[3] 1% ? 1% ? 1% ? 1% ? pd[4] 1% ? 1% ? 1% ? 1% ? pd[5] 1% ? 1% ? 1% ? 1% ? pd[6] 1% ? 1% ? 1% ? 2% ? pd[7] 1% ? 1% ? 1% ? 2% ? table 24. i/o weight (1) (continued) supply segment pad lqfp176 lqfp144/100 weight 5 v weight 3.3 v weight 5 v weight 3.3 v lqfp 176 lqfp 144 lqfp 100 src (2) = 0 src = 1 src = 0 src = 1 src = 0 src = 1 src = 0 src = 1
docid15131 rev 9 73/133 spc560b54x/6x electrical characteristics 132 422 pd[8] 1% ? 1% ? 1% ? 2% ? pb[4] 1% ? 1% ? 1% ? 2% ? pb[5] 1% ? 1% ? 1% ? 2% ? pb[6] 1% ? 1% ? 1% ? 2% ? pb[7] 1% ? 1% ? 1% ? 2% ? pd[9] 1% ? 1% ? 1% ? 2% ? pd[10] 1% ? 1% ? 1% ? 2% ? pd[11] 1% ? 1% ? 1% ? 2% ? table 24. i/o weight (1) (continued) supply segment pad lqfp176 lqfp144/100 weight 5 v weight 3.3 v weight 5 v weight 3.3 v lqfp 176 lqfp 144 lqfp 100 src (2) = 0 src = 1 src = 0 src = 1 src = 0 src = 1 src = 0 src = 1
electrical characteri stics spc560b54x/6x 74/133 docid15131 rev 9 4 ??pb[11]1%?1%????? ??pd[12]11%?13%????? 22 pb[12] 11% ? 13% ? 15% ? 17% ? pd[13] 11% ? 13% ? 14% ? 17% ? pb[13] 11% ? 13% ? 14% ? 17% ? pd[14] 11% ? 13% ? 14% ? 17% ? pb[14] 11% ? 13% ? 14% ? 16% ? pd[15] 11% ? 13% ? 13% ? 16% ? pb[15] 11% ? 13% ? 13% ? 15% ? ??pi[8]10%?12%????? ??pi[9]10%?12%????? ??pi[10]10%?12%????? ??pi[11]10%?12%????? ??pi[12]10%?12%????? ??pi[13]10%?11%????? 2 2 pa[3] 9% ? 11% ? 11% ? 13% ? ? pg[13] 9% 13% 11% 11% 10% 14% 12% 13% ? pg[12] 9% 13% 10% 11% 10% 14% 12% 12% ? ph[0] 6% 8% 7% 7% 6% 9% 7% 8% ? ph[1] 6% 8% 7% 7% 6% 8% 7% 7% ? ph[2] 5% 7% 6% 6% 5% 7% 6% 7% ? ph[3] 5% 7% 5% 6% 5% 7% 6% 6% ? pg[1] 4% ? 5% ? 4% ? 5% ? ? pg[0] 4% 5% 4% 5% 4% 5% 4% 5% table 24. i/o weight (1) (continued) supply segment pad lqfp176 lqfp144/100 weight 5 v weight 3.3 v weight 5 v weight 3.3 v lqfp 176 lqfp 144 lqfp 100 src (2) = 0 src = 1 src = 0 src = 1 src = 0 src = 1 src = 0 src = 1
docid15131 rev 9 75/133 spc560b54x/6x electrical characteristics 132 5 3 ? pf[15] 4% ? 4% ? 4% ? 4% ? ? pf[14] 4% 6% 5% 5% 4% 6% 5% 5% ? pe[13] 4% ? 5% ? 4% ? 5% ? 3 pa[7] 5% ? 6% ? 5% ? 6% ? pa[8] 5% ? 6% ? 5% ? 6% ? pa[9] 6% ? 7% ? 6% ? 7% ? pa[10] 6% ? 8% ? 6% ? 8% ? pa[11] 8% ? 9% ? 8% ? 9% ? pe[12] 8% ? 9% ? 8% ? 9% ? ? pg[14] 8% ? 9% ? 8% ? 9% ? ? pg[15] 8% 11% 9% 10% 8% 11% 9% 10% ? pe[14] 8% ? 9% ? 8% ? 9% ? ? pe[15] 8% 11% 9% 10% 8% 11% 9% 10% ? pg[10] 8% ? 9% ? 8% ? 9% ? ? pg[11] 7% 11% 9% 9% 7% 11% 9% 9% ??ph[11]7%10%9%9%???? ??ph[12]7%10%8%9%???? ??pi[5]7%?8%????? ??pi[4]7%?8%????? 33 pc[3] 6% ? 8% ? 6% ? 8% ? pc[2]6% 8%7%7%6%8%7%7% pa[5]6% 8%7%7%6%8%7%7% pa[6] 5% ? 6% ? 5% ? 6% ? ph[10] 5% 7% 6% 6% 5% 7% 6% 6% pc[1] 5% 19% 5% 13% 5% 19% 5% 13% table 24. i/o weight (1) (continued) supply segment pad lqfp176 lqfp144/100 weight 5 v weight 3.3 v weight 5 v weight 3.3 v lqfp 176 lqfp 144 lqfp 100 src (2) = 0 src = 1 src = 0 src = 1 src = 0 src = 1 src = 0 src = 1
electrical characteri stics spc560b54x/6x 76/133 docid15131 rev 9 4.7 reset electrical ch aracteristics the device implements a dedicated bidirectional reset pin. 6 4 4 pc[0]6% 9%7%8%7%10%8%8% ph[9] 7% ? 8% ? 7% ? 9% ? pe[2] 7% 10% 8% 9% 8% 11% 9% 10% pe[3] 7% 10% 9% 9% 8% 12% 10% 10% pc[5] 7% 11% 9% 9% 8% 12% 10% 11% pc[4] 8% 11% 9% 10% 9% 13% 10% 11% pe[4] 8% 11% 9% 10% 9% 13% 11% 12% pe[5] 8% 11% 10% 10% 9% 14% 11% 12% ? ph[4] 8% 12% 10% 10% 10% 14% 12% 12% ? ph[5] 8% ? 10% ? 10% ? 12% ? ? ph[6] 8% 12% 10% 11% 10% 15% 12% 13% ? ph[7] 9% 12% 10% 11% 11% 15% 13% 13% ? ph[8] 9% 12% 10% 11% 11% 16% 13% 14% 4 pe[6] 9% 12% 10% 11% 11% 16% 13% 14% pe[7] 9% 12% 10% 11% 11% 16% 14% 14% ??pi[3]9%?10%????? ??pi[2]9%?10%????? ??pi[1]9%?10%????? ??pi[0]9%?10%????? 44 pc[12] 8% 12% 10% 11% 12% 18% 15% 16% pc[13] 8% ? 10% ? 13% ? 15% ? pc[8]8% ?10%?13%?15%? pb[2] 8% 11% 9% 10% 13% 18% 15% 16% 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. src: ?slew rate control? bit in siu_pcrx. table 24. i/o weight (1) (continued) supply segment pad lqfp176 lqfp144/100 weight 5 v weight 3.3 v weight 5 v weight 3.3 v lqfp 176 lqfp 144 lqfp 100 src (2) = 0 src = 1 src = 0 src = 1 src = 0 src = 1 src = 0 src = 1
docid15131 rev 9 77/133 spc560b54x/6x electrical characteristics 132 figure 7. start-up reset requirements figure 8. noise filtering on reset signal v il v dd device reset forced by reset v ddmin reset v ih device start-up phase v reset v il v ih v dd filtered by hysteresis filtered by lowpass filter w frst w nfrst hw_rst ?1? ?0? filtered by lowpass filter w frst unknown reset state device under hardware reset
electrical characteri stics spc560b54x/6x 78/133 docid15131 rev 9 table 25. reset electrical characteristics symbol c parameter conditions (1) value unit min typ max v ih sr p input high level cmos ? (schmitt trigger) ? 0.65v dd ?v dd + 0.4 v v il sr p input low level cmos ? (schmitt trigger) ? ? 0.4 ? 0.35v dd v v hys cc c input hysteresis cmos ? (schmitt trigger) ?0.1v dd ?? v v ol cc p output low level push pull, i ol = 2 ma, ? v dd = 5.0 v 10%, pad3v5v = 0 ? (recommended) ? ? 0.1v dd v push pull, i ol = 1 ma, ? v dd = 5.0 v 10%, pad3v5v = 1 (2) ? ? 0.1v dd push pull, i ol = 1 ma, ? v dd = 3.3 v 10%, pad3v5v = 1 ? (recommended) ??0.5 t tr cc d output transition time output pin (3) medium configuration c l = 25 pf, ? v dd = 5.0 v 10%, pad3v5v = 0 ?? 10 ns c l = 50 pf, ? v dd = 5.0 v 10%, pad3v5v = 0 ?? 20 c l = 100 pf, ? v dd = 5.0 v 10%, pad3v5v = 0 ?? 40 c l = 25 pf, ? v dd = 3.3 v 10%, pad3v5v = 1 ?? 12 c l = 50 pf, ? v dd = 3.3 v 10%, pad3v5v = 1 ?? 25 c l = 100 pf, ? v dd = 3.3 v 10%, pad3v5v = 1 ?? 40 w frst sr p reset input filtered pulse ? ? ? 40 ns w nfrst sr p reset input not filtered pulse ? 1000 ? ? ns |i wpu |cc p weak pull-up current absolute value v dd = 3.3 v 10%, pad3v5v = 1 10 ? 150 a dv dd = 5.0 v 10%, pad3v5v = 0 10 ? 150 p v dd = 5.0 v 10%, pad3v5v = 1 (4) 10 ? 250 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. this is a transient configuration duri ng power-up, up to the end of reset phase2 (refer to rgm module section of the device reference manual). 3. c l includes device and package capacitance (c pkg < 5 pf). 4. the configuration pad3v5 = 1 when v dd = 5 v is only transient configuration during power-up. all pads but reset and nexus output (mdox, evto, mcko) are configured in input or in high impedance state.
docid15131 rev 9 79/133 spc560b54x/6x electrical characteristics 132 4.8 power management el ectrical characteristics 4.8.1 voltage regulator electrical characteristics the device implements an internal voltage regulator to generate the low voltage core supply v dd_lv from the high voltage ballast supply v dd_bv . the regulator itself is supplied by the common i/o supply v dd . the following supplies are involved: ? hv: high voltage external power supply for voltage regulator module. this must be provided externally through v dd power pin. ? bv: high voltage external power supply for internal ballast module. this must be provided externally through v dd_bv power pin. voltage values should be aligned with v dd . ? lv: low voltage internal power supply for core, fmpll and flash digital logic. this is generated by the inte rnal voltage regulator but prov ided outside to connect stability capacitor. it is further split into four ma in domains to ensure noise isolation between critical lv modules within the device: ? lv_cor: low voltage supply for the core. it is also used to provide supply for fmpll through double bonding. ? lv_cfla: low voltage supply for code fl ash module. it is supplied with dedicated ballast and shorted to lv_cor through double bonding. ? lv_dfla: low voltage supply for data flash module. it is supplied with dedicated ballast and shorted to lv_cor through double bonding. ? lv_pll: low voltage supply for fmpll. it is shorted to lv_cor through double bonding. figure 9. voltage regula tor capacitance connection c reg1 (lv_cor/lv_dfla) device v ss_lv v dd_bv v dd_lv c dec1 (ballast decoupling) v ss_lv v dd_lv v dd v ss_lv v dd_lv c reg2 (lv_cor/lv_cfla) c reg3 c dec2 device v dd_bv i v dd_lvn v ref v dd voltage regulator v ss v ss_lvn (supply/io decoupling) (lv_cor/lv_pll)
electrical characteri stics spc560b54x/6x 80/133 docid15131 rev 9 the internal voltage regulator requires external capacitance (c regn ) to be connected to the device in order to provide a stable low voltage digital supply to the device. capacitances should be placed on the board as near as possib le to the associated pins. care should also be taken to limit the serial inductance of the board to less than 5 nh. each decoupling capacitor must be placed between each of the three v dd_lv /v ss_lv supply pairs to ensure stable voltage (see section 4.4: recommended operating conditions ). table 26. voltage regulator electrical characteristics symbol c parameter conditions (1) value unit min typ max c regn sr ? internal voltage regulator external capacitance ? 200 ? 500 nf r reg sr ? stability capacitor equivalent serial resistance range: 10 khz to 20 mhz ??0.2w c dec1 sr ? decoupling capacitance (2) ballast v dd_bv /v ss_lv pair: v dd_bv = 4.5 v to 5.5 v 100 (3) 470 (4) ? nf v dd_bv /v ss_lv pair: v dd_bv = 3 v to 3.6 v 400 ? c dec2 sr ? decoupling capacitance regulator supply v dd /v ss pair 10 100 ? nf v mreg cc t main regulator output voltage before exiting from reset ? 1.32 ? v p after trimming 1.16 1.28 ? i mreg sr ? main regulator current provided to v dd_lv domain ??? 150 ma i mregint cc d main regulator module current consumption i mreg = 200 ma ? ? 2 ma i mreg = 0 ma ? ? 1 v lpreg cc p low-power regulator output voltage after trimming 1.16 1.28 ? v i lpreg sr ? low-power regulator current provided to v dd_lv domain ??? 15 ma i lpregint cc d low-power regulator module current consumption i lpreg = 15 ma; ? t a = 55 c ?? 600 a ? i lpreg = 0 ma; ? t a = 55 c ? 5? v ulpreg cc p ultra low power regulator output voltage after trimming 1.16 1.28 ? v i ulpreg sr ? ultra low power regulator current provided to v dd_lv domain ??? 5 ma i ulpregint cc d ultra low power regulator module current consumption i ulpreg = 5 ma; ? t a = 55 c ?? 100 a i ulpreg = 0 ma; ? t a = 55 c ? 2? i dd_bv cc d in-rush average current on v dd_bv during power-up (5) ?? ? 300 (6) ma
docid15131 rev 9 81/133 spc560b54x/6x electrical characteristics 132 4.8.2 low voltage detector electrical characteristics the device implements a power-on reset (por) module to ensure correct power-up initialization, as well as five low volt age detectors (lvds) to monitor the v dd and the v dd_lv voltage while devi ce is supplied: ? por monitors v dd during the power-up phase to ensure device is maintained in a safe reset state (refer to rgm destructive even t status (rgm_des) register flag f_por in device reference manual) ? lvdhv3 monitors v dd to ensure device reset below minimum functional supply (refer to rgm destructive event status (rgm_d es) register flag f_lvd27 in device reference manual) ? lvdhv3b monitors v dd_bv to ensure device reset below minimum functional supply (refer to rgm destructive event status (rgm_des) regi ster flag f_lvd27_vreg in device reference manual) ? lvdhv5 monitors v dd when application uses device in the 5.0 v 10% range (refer to rgm functional event status (rgm_fes) regi ster flag f_lvd45 in device reference manual) ? lvdlvcor monitors power domain no. 1 (refer to rgm destructive event status (rgm_des) register flag f_lvd12_ pd1 in device reference manual) ? lvdlvbkp monitors power doma in no. 0 (refer to rgm destructiv e event status (rgm_des) register flag f_lvd12_ pd0 in device reference manual) note: when enabled, power domain no. 2 is monitored through lvdlvbkp. 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. this capacitance value is driven by the constrai nts of the external voltage regulator supplying the v dd_bv voltage. a typical value is in the range of 470 nf. 3. this value is acceptable to guarantee operation from 4.5 v to 5.5 v. 4. external regulator and capacitance circ uitry must be capable of providing i dd_bv while maintaining supply v dd_bv in operating range. 5. in-rush average current is seen only for short time during power-up and on standby exit (maximum 20 s, depending on external capacitances to be loaded). 6. the duration of the in-rush current depends on the capacitanc e placed on lv pins. bv decoupli ng capacitors must be sized accordingly. refer to i mreg value for minimum amount of current to be provided in cc.
electrical characteri stics spc560b54x/6x 82/133 docid15131 rev 9 figure 10. low voltage detector vs reset 4.9 power consumption table 28 provides dc electrical characteristic s for significant application modes. these values are indicative values; actual consumption depends on the application. v dd v lvdhvxh reset v lvdhvxl table 27. low voltage detector electrical characteristics symbol c parameter conditions (1) value unit min typ max v porup sr p supply for functional por module t a = 25 c, after trimming 1.0 ? 5.5 v v porh cc p power-on reset threshold 1.5 ? 2.6 v lvdhv3h cc t lvdhv3 low voltage detector high threshold ? ? 2.95 v lvdhv3l cc p lvdhv3 low voltage detector low threshold 2.6 ? 2.9 v lvdhv3bh cc p lvdhv3b low voltage detector high threshold ? ? 2.95 v lvdhv3bl cc p lvdhv3b low voltage detector low threshold 2.6 ? 2.9 v lvdhv5h cc t lvdhv5 low voltage detector high threshold ? ? 4.5 v lvdhv5l cc p lvdhv5 low voltage detector low threshold 3.8 ? 4.4 v lvdlvcorl cc p lvdlvcor low voltage detector low threshold 1.08 ? 1.16 v lvdlvbkpl cc p lvdlvbkp low voltage detect or low threshold 1.08 ? 1.16 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified.
docid15131 rev 9 83/133 spc560b54x/6x electrical characteristics 132 table 28. power consumption on vdd_bv and vdd_hv symbol c parameter conditions (1) value unit min typ max i ddmax (2) cc d run mode maximum average current ??115140 (3) ma i ddrun (4) cc t run mode typical average current (5) f cpu = 8 mhz ? 12 ? ma tf cpu = 16 mhz ? 27 ? tf cpu = 32 mhz ? 43 ? pf cpu = 48 mhz ? 56 100 pf cpu = 64 mhz ? 70 125 i ddhalt cc c halt mode current (6) slow internal rc oscillator (128 khz) running t a = 25 c ? 10 18 ma pt a = 125 c ? 17 28 i ddstop cc p stop mode current (7) slow internal rc oscillator (128 khz) running t a = 25 c ? 350 900 (8) a dt a = 55 c ? 750 ? dt a = 85 c ? 2 7 ma dt a = 105 c ? 4 10 pt a = 125 c ? 7 14 i ddstdby2 cc p standby2 mode current (9) slow internal rc oscillator (128 khz) running t a = 25 c ? 30 100 a dt a = 55 c ? 75 ? dt a = 85 c ? 180 700 dt a = 105 c ? 315 1000 pt a = 125 c ? 560 1700 i ddstdby1 cc t standby1 mode current (10) slow internal rc oscillator (128 khz) running t a = 25 c ? 20 60 a dt a = 55 c ? 45 ? dt a = 85 c ? 100 350 dt a = 105 c ? 165 500 dt a = 125 c ? 280 900 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. i ddmax is drawn only from the vdd_bv pin. running consum ption does not include i/os toggling which is highly dependent on the application. the given value is thought to be a worst case value with al l peripherals running, and code fetched from code flash while modify operation ongoing on data flas h. notice that this value c an be significantly reduced by application: switch off not used peripherals (default), reduc e peripheral frequency through internal prescaler, fetch from ram most used functions, use low power mode when possible. 3. higher current may be sunk by device during power-up and standby exit. please refer to in-rush average current in table 26 . 4. i ddrun is drawn only from the vdd_bv pin. run current measur ed with typical application wi th accesses on both flash and ram. 5. only for the ?p? classification: data and code flash in no rmal power. code fetched from ram: serial ips can and lin in loop back mode, dspi as master, pll as system clock (4 x multiplier) peri pherals on (emios/ctu/adc) and running at max frequency, periodic sw/w dg timer reset enabled.
electrical characteri stics spc560b54x/6x 84/133 docid15131 rev 9 4.10 flash memory elect rical characteristics 4.10.1 program/erase characteristics table 29 shows the program and erase characteristics. 6. data flash power down. code flash in low power. sirc 128 khz and firc 16 mhz on. 10 mhz xtal clock. flexcan: instances: 0, 1, 2 on (clocked but not reception or transmission) , instances: 4, 5, 6 clocks gated. linflex: instances: 0, 1, 2 on (clocked but not reception or trans mission), instance: 3 to 9 clocks gated. emios: instance: 0 on (16 channels on pa[0]?pa[11] and pc[12]?pc[15]) with pwm 20 khz, inst ance: 1 clock gated. dspi: instance: 0 (clocked but no communication), instance: 1 to 5 clocks gated. rtc/api on . pit on. stm on. adc1 off. adc0 on but no conversion except two analog watchdogs. 7. only for the ?p? classification: no clock, firc 16 mhz off, sirc 128 khz on, pll off, hpvreg off, ulpvreg/lpvreg on. all possible peripherals off and clock gated. flash in power down mode. 8. when going from run to stop mode and the core consumption is > 6 ma, it is normal operation for the main regulator module to be kept on by the on-chip current monitoring circuit. this is most likely to occur with junction temperatures exceeding 125 c and under these circumstan ces, it is possible for the current to initially exceed the maximum stop specification by up to 2 ma. after enter ing stop, the application junction temperat ure will reduce to the ambient level and the main regulator will be automatically switc hed off when the load current is below 6 ma. 9. only for the ?p? classificati on: ulpreg on, hp/lpvreg off, 32 kb ram on, dev ice configured for minimum consumption, all possible modules switched off. 10. ulpreg on, hp/lpvreg off, 8 kb ram on, device configured for minimum consumption, all possible modules switched off. table 29. program and erase specifications symbol c parameter conditions value unit min typ (1) initial max (2) max (3) t dwprogram c c c double word (64 bits) program time (4) code flash ? 18 50 500 s data flash 22 t 16kpperase 16 kb block preprogram and erase time code flash ? 200 500 5000 ms data flash 300 t 32kpperase 32 kb block preprogram and erase time code flash ? 300 600 5000 ms data flash 400 t 128kpperase 128 kb block preprogram and erase time code flash ? 600 1300 7500 ms data flash 800 t esus d erase suspend latency ? ? ? 30 30 s t esrt c erase suspend request rate (5) code flash 20 ? ? ? ms data flash 10 ? ? ? 1. typical program and erase times assume nominal supply values and operation at 25 c. all times are subject to change pending device characterization. 2. initial factory condition: < 100 program/e rase cycles, 25 c, typical supply voltage. 3. the maximum program and erase times occur after the specif ied number of program/erase cycles. these maximum values are characterized but not guaranteed. 4. actual hardware programming times. this does not include software overhead. 5. time between erase suspend resume and the next erase suspend request.
docid15131 rev 9 85/133 spc560b54x/6x electrical characteristics 132 ecc circuitry provides correction of single bit faults and is used to improve further automotive reliability re sults. some units will experience si ngle bit correc tions throughout the life of the product with no impact to product reliability. 4.10.2 flash power supply dc characteristics table 32 shows the power supply dc characteristics on external supply. table 30. flash module life symbol c parameter conditions value unit min typ max p/e cc c number of program/erase cycles per block for 16 kb blocks over the operating temperature range (t j ) ? 100000 ? ? cycles p/e cc c number of program/erase cycles per block for 32 kb blocks over the operating temperature range (t j ) ? 10000 100000 ? cycles p/e cc c number of program/erase cycles per block for 128 kb blocks over the operating temperature range (t j ) ? 1000 100000 ? cycles retention cc c minimum data retention at 85 c average ambient temperature (1) blocks with 0?1000 p/e cycles 20 ? ? years blocks with 1001?10000 p/e cycles 10 ? ? years blocks with 10001?100000 p/e cycles 5??years 1. ambient temperature averaged over duration of applicati on, not to exceed recommended product operating temperature range. table 31. flash read access timing symbol c parameter conditions (1) max unit f read cc p maximum frequency for flash reading 2 wait states 64 mhz c 1 wait state 40 c 0 wait states 20 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified.
electrical characteri stics spc560b54x/6x 86/133 docid15131 rev 9 4.10.3 start-up/switch-off timings 4.11 electromagnetic compati bility (emc) characteristics susceptibility tests are perfor med on a sample basis during product characterization. 4.11.1 designing hardened soft ware to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. table 32. flash power supply dc electrical characteristics symbol parameter conditions (1) value unit min typ max i cfread cc sum of the current consumption on v dd_hv and v dd_bv on read access flash module read f cpu = 64 mhz code flash ? ? 33 ma i dfread data flash ? ? 33 i cfmod cc sum of the current consumption on v dd_hv and v dd_bv on matrix modification (program/erase) program/erase on-going while reading flash registers f cpu = 64 mhz code flash ? ? 52 ma i dfmod data flash ? ? 33 i cflpw cc sum of the current consumption on v dd_hv and v dd_bv during flash low power mode ? code flash ? ? 1.1 ma i dflpw data flash ? ? 900 a i cfpwd cc sum of the current consumption on v dd_hv and v dd_bv during flash power down mode ? code flash ? ? 150 a i dfpwd data flash ? ? 150 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 to 125 c, unless otherwise specified. table 33. start-up time/switch-off time symbol c parameter conditions (1) value unit min typ max t flarstexit cc t delay for flash module to exit reset mode ? ? ? 125 s t flalpexit cc t delay for flash module to exit low-power mode ? ? ? 0.5 t flapdexit cc t delay for flash module to exit power-down mode ? ? ? 30 t flalpentry cc t delay for flash module to enter low-power mode ? ? ? 0.5 t flapdentry cc t delay for flash module to enter power-down mode ? ? ? 1.5 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified.
docid15131 rev 9 87/133 spc560b54x/6x electrical characteristics 132 therefore it is recommended that the us er apply emc software optimization and prequalification tests in re lation with the emc level requested for the application. ? software recommendations ?? the software flowchart must include the management of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) ? prequalification trials ?? most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note software techniques for improving microcontroller emc performance (an1015)). 4.11.2 electromagnetic interference (emi) the product is monitored in terms of emission based on a typical application. this emission test conforms to the iec61967-1 standard, wh ich specifies the genera l conditions for emi measurements. 4.11.3 absolute maximum ratings (electrical sensitivity) based on two different tests (esd and lu) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. table 34. emi radiated emission measurement (1)(2) symbol c parameter conditions value unit min typ max ? sr ? scan range ? 0.15 0 1000 mhz f cpu sr ? operating frequency ? ? 64 ? mhz v dd_lv sr ? lv operating voltages ??1.28?v s emi cc t peak level v dd = 5 v, t a = 25 c, ? lqfp144 package test conforming to iec 61967-2, f osc = 8 mhz/f cpu = 64 mhz no pll frequency modulation ??18 db v 2% pll frequency modulation ??14 db v 1. emi testing and i/o port waveforms per iec 61967-1, -2, -4. 2. for information on conducted emission and susceptibility measurement (norm ie c 61967-4), please contact your local marketing representative.
electrical characteri stics spc560b54x/6x 88/133 docid15131 rev 9 4.11.3.1 electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts ? (n + 1) supply pin). this test conforms to the aec-q100-002/-003/-011 standard. for more details, refer to the application note electrostatic discharge sensitivity measurement (an1181). 4.11.3.2 static latch-up (lu) two complementary static te sts are required on six pa rts to assess the latch-up performance: ? a supply overvoltage is applied to each power supply pin. ? a current injection is applied to each input, output and configurable i/o pin. these tests are compliant with the eia/jesd 78 ic latch-up standard. 4.12 fast external crys tal oscillator (4 to 16 mhz) electrical characteristics the device provides an o scillator/resona tor driver. figure 11 describes a simple model of the internal oscillator driver and provides an example of a co nnection for an oscillator or a resonator. table 37 provides the parameter description of 4 mhz to 16 mhz crystals used for the design simulations. table 35. esd absolute maximum ratings (1)(2) symbol ratings conditions class max value (3) unit v esd(hbm) electrostatic discharge voltage (human body model) t a = 25 c conforming to aec-q100-002 h1c 2000 v v esd(mm) electrostatic discharge voltage (machine model) t a = 25 c conforming to aec-q100-003 m2 200 v esd(cdm) electrostatic discharge voltage (charged device model) t a = 25 c conforming to aec-q100-011 c3a 500 750 (corners) 1. all esd testing is in conformity with cdf-aec-q100 stress test qualification for automotive grade integrated circuits. 2. a device will be defined as a failure if after exposure to esd pulses the device no longer meets the device specification requirements. complete dc parametric and functional test ing shall be performed per applic able device specification at room temperature followed by hot temperature, unles s specified otherwise in the device specification. 3. data based on characterization re sults, not tested in production table 36. latch-up results symbol parameter conditions class lu static latch-up class t a = 125 c ? conforming to jesd 78 ii level a
docid15131 rev 9 89/133 spc560b54x/6x electrical characteristics 132 figure 11. crystal oscillator and resonator connection scheme c2 c1 crystal xtal extal resonator xtal extal device device device xtal extal i r v dd 2. a series resistor may be required, accordi ng to crystal oscillator supplier recommendations. 1. xtal/extal must not be directly used to drive external circuits notes: table 37. crystal description nominal frequency (mhz) ndk crystal reference crystal equivalent series resistance esr ? crystal motional capacitance (c m ) ff crystal motional inductance (l m ) mh load on xtalin/xtalout c1 = c2 (pf) (1) shunt capacitance between xtalout and xtalin c0 (2) (pf) 4 nx8045gb 300 2.68 591.0 21 2.93 8 nx5032ga 300 2.46 160.7 17 3.01 10 150 2.93 86.6 15 2.91 12 120 3.11 56.5 15 2.93 16 120 3.90 25.3 10 3.00 1. the values specified for c1 and c2 are the same as used in simulations. it should be ensured that the testing includes all the parasitics (from the board, probe, crystal, etc. ) as the ac / transient behavior depends upon them. 2. the value of c0 specified here includes 2 pf additional ca pacitance for parasitics (to be seen with bond-pads, package, etc.).
electrical characteri stics spc560b54x/6x 90/133 docid15131 rev 9 figure 12. fast external crystal oscillator (4 to 16 mhz) timing diagram v mxoscop t mxoscsu v xtal v mxosc valid internal clock 90% 10% 1/f mxosc s_mtrans bit (me_gs register) 1 0 table 38. fast external crystal oscillator (4 to 16 mhz) electrical characteristics symbol c parameter conditions (1) value unit min typ max f fxosc s r ? fast external crystal oscillator frequency ? 4.0 ? 16.0 mhz g mfxosc c c c fast external crystal oscillator transconductance v dd = 3.3 v 10%, ? pad3v5v = 1 ? oscillator_margin = 0 2.2 ? 8.2 ma/ v c c p v dd = 5.0 v 10%, ? pad3v5v = 0 ? oscillator_margin = 0 2.0 ? 7.4 c c c v dd = 3.3 v 10%, ? pad3v5v = 1 ? oscillator_margin = 1 2.7 ? 9.7 c c c v dd = 5.0 v 10%, ? pad3v5v = 0 ? oscillator_margin = 1 2.5 ? 9.2 v fxosc c c t oscillation amplitude at extal f osc = 4 mhz, ? oscillator_margin = 0 1.3 ? ? v f osc = 16 mhz, ? oscillator_margin = 1 1.3 ? ? v fxoscop c c c oscillation operating point ? ? 0.95 ? v
docid15131 rev 9 91/133 spc560b54x/6x electrical characteristics 132 4.13 slow external crystal osc illator (32 khz) electrical characteristics the device provides a low powe r oscillator/reso nator driver. figure 13. crystal oscillator and resonator connection scheme i fxosc (2) c c t fast external crystal oscillator consumption ??23ma t fxoscsu c c t fast external crystal oscillator start-up time f osc = 4 mhz, ? oscillator_margin = 0 ?? 6 ms f osc = 16 mhz, ? oscillator_margin = 1 ??1.8 v ih s r p input high level cmos ? (schmitt trigger) oscillator bypass mode 0.65v dd ? v dd + 0. 4 v v il s r p input low level cmos ? (schmitt trigger) oscillator bypass mode ? 0.4 ? 0.35v dd v 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. stated values take into account only analog module cons umption but not the digital c ontributor (clock tree and enabled peripherals). table 38. fast external crystal oscillator (4 to 16 mhz) electrical characteristics (continued) symbol c parameter conditions (1) value unit min typ max osc32k_xtal osc32k_extal device c2 c1 crystal osc32k_xtal osc32k_extal r p resonator device note : osc32_xtal/osc32_extal must not be di rectly used to drive external circuits
electrical characteri stics spc560b54x/6x 92/133 docid15131 rev 9 figure 14. equivalent circuit of a quartz crystal c0 c2 c1 c2 r m c1 l m c m crystal table 39. crystal motional characteristics (1) symbol parameter conditions value unit min typ max l m motional inductance ? ? 11.796 ? kh c m motional capacitance ? ? 2 ? ff c1/c2 load capacitance at osc32k_xtal and osc32k_extal with respect to ground (2) ? 18 ? 28 pf r m (3) motional resistance ac coupled at c0 = 2.85 pf (4) ??65 kw ac coupled at c0 = 4.9 pf (4) ??50 ac coupled at c0 = 7.0 pf (4) ??35 ac coupled at c0 = 9.0 pf (4) ??30 1. the crystal used is epson toyocom mc306. 2. this is the recommended range of load capacitance at os c32k_xtal and osc32k_extal with respect to ground. it includes all the parasitics due to board traces, crystal and package. 3. maximum esr (r m ) of the crystal is 50 k ?? 4. c0 includes a parasitic capacitance of 2.0 pf between osc32k_xtal and osc32k_extal pins.
docid15131 rev 9 93/133 spc560b54x/6x electrical characteristics 132 figure 15. slow external crystal os cillator (32 khz) timing diagram 4.14 fmpll electrical characteristics the device provides a frequency modulated phase locked loop (fmpll) module to generate a fast system clock fr om the main os cillator driver. oscon bit (osc_ctl register) t lpxosc32ksu 1 v osc32k_xtal v lpxosc32k valid internal clock 90% 10% 1/f lpxosc32k 0 table 40. slow external crystal oscillator (32 khz) electrical characteristics symbol c parameter conditions (1) value unit min typ max f sxosc s r ? slow external crystal oscillator frequency ?32 32.76 8 40 khz v sxosc c c t oscillation amplitude ? ? 2.1 ? v i sxoscbias c c t oscillation bias current ? 2.5 a i sxosc c c t slow external crystal oscillator consumption ???8a t sxoscsu c c t slow external crystal oscillator start-up time ???2 (2) s 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. values are specified for no neighbor gpio pin activity. if oscill ator is enabled (osc32k_xtal and osc32k_extal pins), neighboring pins should not toggle. 2. start-up time has been measured with epson toyocom mc 306 crystal. variation may be seen with other crystal.
electrical characteri stics spc560b54x/6x 94/133 docid15131 rev 9 4.15 fast internal rc o scillator (16 mhz) electr ical characteristics the device provides a 16 mhz main internal rc oscillator. this is used as the default clock at the power-up of the device. table 41. fmpll electrical characteristics symbol c parameter conditions (1) value unit min typ max f pllin sr ? fmpll reference clock (2) ?4?64mhz ? pllin sr ? fmpll reference clock duty cycle (2) ?40?60% f pllout cc p fmpll output clock frequency ? 16 ? 64 mhz f vco (3) cc p vco frequency without frequency modulation ?256?512 mhz p vco frequency with frequency modulation ? 245.76 ? 532.48 f cpu sr ? system clock frequency ? ? ? 64 mhz f free cc p free-running frequency ? 20 ? 150 mhz t lock cc p fmpll lock time stable oscillator (f pllin = 16 mhz) 40 100 s ? t stjit cc ? fmpll short term jitter (4) f sys maximum ?4 ? 4 % ? t ltjit cc ? fmpll long term jitter f pllclk at 64 mhz, 4000 cycles ? ? 10 ns i pll cc c fmpll consumption t a = 25 c ? ? 4 ma 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2. pllin clock retrieved directly from fxos c clock. input characteristics are granted when oscillator is used in functional mode. when bypass mode is used, osci llator input clock should verify f pllin and ? pllin . 3. frequency modulation is considered 4%. 4. short term jitter is measured on t he clock rising edge at cycle n and n+4. table 42. fast internal rc oscillator (16 mhz) electrical characteristics symbol c parameter conditions (1) value unit min typ max f firc cc p fast internal rc oscillator high frequency t a = 25 c, trimmed ? 16 ? mhz sr ? ? 12 20 i fircrun (2) cc t fast internal rc oscillator high frequency current in running mode t a = 25 c, trimmed ? ? 200 a i fircpwd cc d fast internal rc oscillator high frequency current in power down mode t a = 25 c ? ? 10 a
docid15131 rev 9 95/133 spc560b54x/6x electrical characteristics 132 4.16 slow internal rc oscillator (128 khz) electrical characteristics the device provides a 128 khz low power internal rc oscillator. this can be used as the reference clock for the rtc module. i fircstop cc t fast internal rc oscillator high frequency and system clock current in stop mode t a = 25 c sysclk = off ? 500 ? a sysclk = 2 mhz ? 600 ? sysclk = 4 mhz ? 700 ? sysclk = 8 mhz ? 900 ? sysclk = 16 mhz ? 1250 ? t fircsu cc c fast internal rc oscillator start- up time v dd = 5.0 v 10% ? 1.1 2.0 s ? fircpre cc c fast internal rc oscillator precision after software trimming of f firc t a = 25 c ? 1? 1% ? firctrim cc c fast internal rc oscillator trimming step t a = 25 c ? 1.6 % ? fircvar cc c fast internal rc oscillator variation over temperature and supply with respect to f firc at t a = 25 c in high-frequency configuration ? ? 5? 5% 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. this does not include consumpt ion linked to clock tree toggling and peripher als consumption when rc oscillator is on. table 42. fast internal rc oscillator (16 mhz) electrical characteristics (continued) symbol c parameter conditions (1) value unit min typ max table 43. slow internal rc oscillator (128 khz) electrical characteristics symbol c parameter conditions (1) value unit min typ max f sirc cc p slow internal rc oscillator low frequency t a = 25 c, trimmed ? 128 ? khz sr ? ? 100 ? 150 i sirc (2) cc c slow internal rc oscillator low frequency current t a = 25 c, trimmed ? ? 5 a t sircsu cc p slow internal rc oscillator start-up time t a = 25 c, v dd = 5.0 v 10% ? 8 12 s
electrical characteri stics spc560b54x/6x 96/133 docid15131 rev 9 4.17 adc electrical characteristics 4.17.1 introduction the device provides two successive approx imation register (sar) analog-to-digital converters (10-bit and 12-bit). ? sircpre cc c slow internal rc oscillator precision after software trimming of f sirc t a = 25 c ? 2? 2 % ? sirctrim cc c slow internal rc oscillator trimming step ??2.7? ? sircvar cc c slow internal rc oscillator variation in temperature and supply with respect to f sirc at t a = 55 c in high frequency configuration high frequency configuration ? 10 ? 10 % 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. this does not include consumpt ion linked to clock tree toggling and peripher als consumption when rc oscillator is on. table 43. slow internal rc oscillator (128 khz) electrical characteristics (continued) symbol c parameter conditions (1) value unit min typ max
docid15131 rev 9 97/133 spc560b54x/6x electrical characteristics 132 figure 16. adc_0 characteristic and error definitions 4.17.2 input impedance and adc accuracy in the following analysis, the input circui t corresponding to t he precise channels is considered. to preserve the accuracy of the a/d converter, it is necessary that analog input pins have low ac impedance. placing a capacitor with good high frequency characteristics at the input pin of the device can be effect ive: the capacitor should be as large as possible, ideally infinite. this capacitor contri butes to attenuating the noise present on the input pin; furthermore, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. a real filter can typically be obtained by usi ng a series resistance with a capacitor on the input pin (simple rc filter). the rc filtering ma y be limited according to the value of source (2) (1) (3) (4) (5) offset error (e o ) offset error (e o ) gain error (e g ) 1 lsb (ideal) 1023 1022 1021 1020 1019 1018 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve 1 lsb ideal = v dd_adc / 1024 v in(a) (lsb ideal ) code out
electrical characteri stics spc560b54x/6x 98/133 docid15131 rev 9 impedance of the transducer or circuit supplying the analog signal to be measured. the filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivale nt input impedance of the adc itself. in fact a current sink contributor is repres ented by the charge sharing effects with the sampling capacitance: being c s and c p2 substantially two switch ed capacitances, with a frequency equal to the conversion rate of the adc, it can be seen as a resistive path to ground. for instance, assuming a conversion rate of 1 mhz, with c s +c p2 equal to 3 pf, a resistance of 330 k ? is obtained (r eq = 1 / (f c (c s +c p2 )), where f c represents the conversion rate at the considered channel). to minimize the error induced by the voltage partitioning between this resistance (sampled voltage on c s +c p2 ) and the sum of r s + r f , the external circuit must be designed to respect the equation 4 : equation 4 equation 4 generates a constraint for external network design, in particular on a resistive path. figure 17. input equivalent ci rcuit (precise channels) v a r s r f + r eq --------------------- ? 1 2 -- -lsb ? r s source impedance r f filter resistance cf filter capacitance r l current limiter resistance r sw1 channel selection switch impedance r ad sampling switch impedance c p pin capacitance (two contributions, c p1 and c p2 ) c s sampling capacitance c p1 r ad channel selection v a
docid15131 rev 9 99/133 spc560b54x/6x electrical characteristics 132 figure 18. input equivalent circuit (extended channels) a second aspect involving the capacitance network shall be c onsidered. assuming the three capacitances c f , c p1 and c p2 are initially charged at the source voltage v a (refer to the equivalent circuit reported in figure 17 ): a charge sharing phenomenon is installed when the sampling phase is started (a/d switch close). figure 19. transient behavior during sampling phase in particular two different transient periods can be distinguished: r f c f r s r l r sw1 c p3 c s v dd sampling source filter current limiter external circuit internal circuit scheme r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw channel selection switch impedance (two contributions r sw1 and r sw2 ) r ad sampling switch impedance c p pin capacitance (three contributions, c p1 , c p2 and c p3 ) c s sampling capacitance c p1 r ad channel selection v a c p2 extended r sw2 switch v a v a1 v a2 t t s v cs voltage transient on c s ? v < ? 0.5 lsb ? 1 2 ? 1 < (r sw + r ad ) c s << t s ? 2 = r l (c s + c p1 + c p2 )
electrical characteri stics spc560b54x/6x 100/133 docid15131 rev 9 1. a first and quick charge transfer from the internal capacitance c p1 and c p2 to the sampling capacitance c s occurs (c s is supposed initially co mpletely discharged): considering a worst case (since the time co nstant in reality would be faster) in which c p2 is reported in parallel to c p1 (call c p = c p1 + c p2 ), the two capacitances c p and c s are in series, and the time constant is equation 5 equation 5 can again be simplified considering only c s as an additional worst condition. in reality, the transient is fa ster, but the a/d converter circuitry has been designed to be robust also in the very worst case: the sampling time t s is always much longer than the internal time constant: equation 6 the charge of c p1 and c p2 is redistributed also on c s , determining a new value of the voltage v a1 on the capacitance according to equation 7 : equation 7 2. a second charge transfer involves also c f (that is typically bigger than the on-chip capacitance) through the resistance r l : again considering the worst case in which c p2 and c s were in parallel to c p1 (since the time constant in reality would be faster), the time constant is: equation 8 in this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time t s , a constraints on r l sizing is obtained: equation 9 adc_0 (10-bit) equation 10 adc_1 (12-bit) of course, r l shall be sized also according to the current limitation constraints, in combination with r s (source impedance) and r f (filter resistance). being c f definitively bigger than c p1 , c p2 and c s , then the final voltage v a2 (at the end of the charge transfer transient ) will be much higher than v a1 . equation 11 must be respected (charge balance assuming now c s already charged at v a1 ): ? 1 r sw r ad + ?? = c p c s ? c p c s + --------------------- ? ? 1 r sw r ad + ?? ? c s t s ? ? v a1 c s c p1 c p2 ++ ?? ? v a c p1 c p2 + ?? ? = ? 2 r l ? c s c p1 c p2 ++ ?? ? ? 2 ? 8.5 r l c s c p1 c p2 ++ ?? ? ? = t s ? 10 ? 2 ? 10 r l c s c p1 c p2 ++ ?? ? ? = t s ?
docid15131 rev 9 101/133 spc560b54x/6x electrical characteristics 132 equation 11 the two transients above are not influenced by the voltage source that, due to the presence of the r f c f filter, is not able to provide the extra charge to compensate the voltage drop on c s with respect to the ideal source v a ; the time constant r f c f of the filter is very high with respect to the sampling time (t s ). the filter is typically des igned to act as antialiasing. figure 20. spectral representation of input signal calling f 0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the antialiasing filter, f f ), according to the nyquist theorem the conversion rate f c must be at least 2f 0 ; it means that the constant ti me of the filter is greater than or at least equal to twice the conversion period (t c ). again the conversion period t c is longer than the sampling time t s , which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter r f c f is definitively much higher than the sampling time t s , so the charge level on c s cannot be modified by the analog sign al source during the time in which the sampling switch is closed. the considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage drop on c s ; from the two charge balance equations above, it is simple to derive equation 12 between the ideal and real sampled voltage on c s : equation 12 from this formula, in the worst case (when v a is maximum, that is for instance 5 v), assuming to accept a maximum error of half a count, a constraint is evident on c f value: equation 13 adc_0 (10-bit) v a2 c s c p1 c p2 c f +++ ?? ? v a c f ? v a1 +c p1 c p2 +c s + ?? ? = f 0 f analog source bandwidth (v a ) f 0 f sampled signal spectrum (f c = conversion rate) f c f anti-aliasing filter (f f = rc filter pole) f f 2 f 0 < f c (nyquist) f f = f 0 (anti-aliasing filtering condition) t c < 2 r f c f (conversion rate vs. filter pole) noise v a2 v a ----------- - c p1 c p2 +c f + c p1 c p2 +c f c s ++ ------------------------------------------------------- - = c f 2048 c s ? ?
electrical characteri stics spc560b54x/6x 102/133 docid15131 rev 9 equation 14 adc_1 (12-bit) 4.17.3 adc electrical characteristics c f 8192 c s ? ? table 44. adc input leakage current symbol c parameter conditions value unit min typ max i lkg cc d input leakage current t a = ? 40 c no current injection on adjacent pin ?170 na dt a = 25 c ? 1 70 dt a = 85 c 3 100 dt a = 105 c ? 8 200 pt a = 125 c ? 45 400 table 45. adc_0 conversion characteristics (10-bit adc_0) symbol c parameter conditions (1) value unit min typ max v ss_adc0 sr ? voltage on vss_hv_adc0 (adc_0 reference) pin with respect to ground (v ss ) (2) ? ? 0.1 ? 0.1 v v dd_adc0 sr ? voltage on vdd_hv_adc pin (adc reference) with respect to ground (v ss ) ?v dd ?? 0.1 ? v dd + 0.1 v v ainx sr ? analog input voltage (3) ? v ss_adc0 ?? 0.1 ? v dd_adc0 + 0.1 v i adc0pwd sr ? adc_0 consumption in power down mode ???50a i adc0run sr ? adc_0 consumption in running mode ???5ma f adc0 sr ? adc_0 analog frequency ? 6? 32 + 4% mhz ? adc0_sys sr ? adc_0 digital clock duty cycle (ipg_clk) adclksel = 1 (4) 45 ? 55 % t adc0_pu sr ? adc_0 power up delay ? ?? 1.5 s t adc0_s cc t sampling time (5) f adc = 32 mhz, ? inpsamp = 17 0.5 ? s f adc = 6 mhz, ? inpsamp = 255 ??42 t adc0_c cc p conversion time (6) f adc = 32 mhz, ? inpcmp = 2 0.625 ? ? s c s cc d adc_0 input sampling capacitance ??? 3 pf
docid15131 rev 9 103/133 spc560b54x/6x electrical characteristics 132 c p1 cc d adc_0 input pin capacitance 1 ? ? ? 3 pf c p2 cc d adc_0 input pin capacitance 2 ??? 1 pf c p3 cc d adc_0 input pin capacitance 3 ? ? ? 1 pf r sw1 cc d internal resistance of analog source ??? 3 k ? r sw2 cc d internal resistance of analog source ? ? ? 2 k ? r ad cc d internal resistance of analog source ??? 2 k ? i inj sr ? input current injection current injection on one adc_0 input, different from the converted one v dd = ? 3.3 v 10% ? 5? 5 ma v dd = ? 5.0 v 10% ? 5 ? 5 | inl | cc t absolute integral nonlinearity no overload ? 0.5 1.5 lsb | dnl | cc t absolute differential nonlinearity no overload ? 0.5 1.0 lsb | e o | cc t absolute offset error ? ? 0.5 ? lsb | e g | cc t absolute gain error ?? 0.6 ? lsb tuep cc p total unadjusted error (7) for precise channels, input only pins without current injection ? 2 0.6 2 lsb t with current injection ? 3 ? 3 tuex cc t total unadjusted error (7) for extended channel without current injection ? 3 1 3 lsb t with current injection ? 4 4 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. analog and digital v ss must be common (to be tied together externally). 3. v ainx may exceed v ss_adc0 and v dd_adc0 limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped resp ectively to 0x000 or 0x3ff. 4. duty cycle is ensured by using system clock without prescaling. when adclksel = 0, the duty cycle is ensured by internal divider by 2. 5. during the sampling time the input capacitance c s can be charged/discharged by the external source. the internal resistance of the analog source must allow the capa citance to reach its final voltage level within t adc0_s . after the end of the sampling time t adc0_s , changes of the analog input voltage have no effect on the conversion result. values for the sampling clock t adc0_s depend on programming. 6. this parameter does not include the sampling time t adc0_s , but only the time for determining the digital result and the time to load the result?s register with the conversion result. 7. total unadjusted error: the maximum error that occurs without adjusting offset and gain errors. this error is a combination of offset, gain and integral linearity errors. table 45. adc_0 conversion characteristics (10-bit adc_0) (continued) symbol c parameter conditions (1) value unit min typ max
electrical characteri stics spc560b54x/6x 104/133 docid15131 rev 9 figure 21. adc_1 characteristic and error definitions (2) (1) (3) (4) (5) offset error (e o ) offset error (e o ) gain error (e g ) 1 lsb (ideal) 4095 4094 4093 4092 4091 4090 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 409040914092409340944095 (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve 1 lsb ideal = v dd_adc / 4096 v in(a) (lsb ideal ) code out table 46. adc_1 conversion characteristics (12-bit adc_1) symbol c parameter conditions (1) value unit min typ max v ss_adc1 sr ? voltage on vss_hv_adc1 (adc_1 reference) pin with respect to ground (v ss ) (2) ??0.1?0.1v v dd_adc1 sr ? voltage on vdd_hv_adc1 pin (adc_1 reference) with respect to ground (v ss ) ?v dd ? 0.1 ? v dd + 0.1 v v ainx sr ? analog input voltage (3) ? v ss_adc1 ? 0.1 ? v dd_adc1 + 0.1 v
docid15131 rev 9 105/133 spc560b54x/6x electrical characteristics 132 i adc1pwd sr ? adc_1 consumption in power down mode ???50a i adc1run sr ? adc_1 consumption in running mode ???6ma f adc1 sr ? adc_1 analog frequency v dd = 3.3 v 3.33 ? 20 + 4% mhz v dd = 5 v 3.33 ? 32 + 4% t adc1_pu sr ? adc_1 power up delay ? ? ? 1.5 s t adc1_s cc t sampling time (4) v dd = 3.3 v f adc1 = 20 mhz, ? inpsamp = 12 600 ? ? ns sampling time (4) v dd = 5.0 v f adc1 = 32 mhz, ? inpsamp = 17 500 ? ? sampling time (4) v dd = 3.3 v f adc1 = 3.33 mhz, ? inpsamp = 255 ??76.2 s sampling time (4) v dd = 5.0 v f adc1 = 3.33 mhz, ? inpsamp = 255 ??76.2 t adc1_c cc p conversion time (5) v dd = 3.3 v f adc1 = 20 mhz, ? inpcmp = 0 2.4 ? ? s conversion time (5) v dd = 5.0 v f adc 1 = 32 mhz, ? inpcmp = 0 1.5 ? ? s conversion time (5) v dd = 3.3 v f adc 1 = 13.33 mhz, ? inpcmp = 0 ??3.6 s conversion time (5) v dd = 5.0 v f adc1 = 13.33 mhz, ? inpcmp = 0 ??3.6 s ? adc1_sys sr ? adc_1 digital clock duty cycle adclksel = 1 (6) 45 ? 55 % c s cc d adc_1 input sampling capacitance ???5pf c p1 cc d adc_1 input pin capacitance 1 ???3pf c p2 cc d adc_1 input pin capacitance 2 ???1pf c p3 cc d adc_1 input pin capacitance 3 ???1.5pf r sw1 cc d internal resistance of analog source ???1k ? r sw2 cc d internal resistance of analog source ???2k ? r ad cc d internal resistance of analog source ???0.3k ? table 46. adc_1 conversion characteristics (12-bit adc_1) (continued) symbol c parameter conditions (1) value unit min typ max
electrical characteri stics spc560b54x/6x 106/133 docid15131 rev 9 i inj sr ? input current injection current injection on one adc_1 input, different from the converted one v dd = 3.3 v 10% ?5 ? 5 ma v dd = 5.0 v 10% ?5 ? 5 | inlp | cc t absolute integral nonlinearity ? precise channels no overload ? 1 3 lsb | inlx | cc t absolute integral nonlinearity ? extended channels no overload ? 1.5 5 lsb | dnl | cc t absolute differential nonlinearity no overload ? 0.5 1 lsb | e o | cc t absolute offset error ? ? 2 ? lsb | e g | cc t absolute gain error ? ? 2 ? lsb tuep (7) cc p total unadjusted error for precise channels, input only pins without current injection ?6 ? 6 lsb t with current injection ?8 ? 8 tuex (7) cc t total unadjusted error for extended channel without current injection ?10 ? 10 lsb t with current injection ?12 ? 12 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 to 125 c, unless otherwise specified 2. analog and digital v ss must be common (to be tied together externally). 3. v ainx may exceed v ss_adc1 and v dd_adc1 limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped res pectively to 0x000 or 0xfff. 4. during the sampling time the input capacitance c s can be charged/discharged by the external source. the internal resistance of the analog source must allow the capaci tance to reach its final voltage level within t adc1_s . after the end of the sampling time t adc1_s , changes of the analog input voltage have no effe ct on the conversion result. values for the sampling clock t adc1_s depend on programming. 5. this parameter does not include the sampling time t adc1_s , but only the time for determining the digital result and the time to load the result?s register with the conversion result. 6. duty cycle is ensured by using system clock without prescaling. when adclksel = 0, the duty cycle is ensured by internal divider by 2. 7. total unadjusted error: the maximum error that occurs wi thout adjusting offset and gain errors. this error is a combination of offset, gain and integral linearity errors. table 46. adc_1 conversion characteristics (12-bit adc_1) (continued) symbol c parameter conditions (1) value unit min typ max
docid15131 rev 9 107/133 spc560b54x/6x electrical characteristics 132 4.18 on-chip peripherals 4.18.1 current consumption table 47. on-chip peripherals current consumption (1) symbol c parameter conditions typical value (2) unit i dd_bv(can) cc t can (flexcan) supply current on v dd_bv bitrate: 500 kbyte/s total (static + dynamic) consumption: ? flexcan in loop-back mode ? xtal at 8 mhz used as can engine clock source ? message sending period is 580 s 8 * f periph + 85 a bitrate: 125 kbyte/s 8 * f periph + 27 i dd_bv(emios) cc t emios supply current on v dd_bv static consumption: ? emios channel off ? global prescaler enabled 29 * f periph a dynamic consumption: ? it does not change varying the frequency (0.003 ma) 3 i dd_bv(sci) cc t sci (linflex) supply current on v dd_bv total (static + dynamic) consumption: ? lin mode ? baudrate: 20 kbyte/s 5 * f periph + 31 a i dd_bv(spi) cc t spi (dspi) supply current on v dd_bv ballast static consumption (only clocked) 1 a ballast dynamic consumption (continuous communication): ? baudrate: 2 mbit/s ? transmission every 8 s ? frame: 16 bits 16 * f periph i dd_bv (adc_0/adc_1) cc t adc_0/adc_1 supply current on v dd_bv v dd = 5.5 v ballast static consumption (no conversion) (3) 41 * f periph a ballast dynamic consumption (continuous conversion) (3) 46 * f periph i dd_hv_adc0 cc t adc_0 supply current on v dd_hv_adc0 v dd = 5.5 v analog static consumption (no conversion) 200 a analog dynamic consumption (continuous conversion) 3ma i dd_hv_adc1 cc t adc_1 supply current on v dd_hv_adc1 v dd = 5.5 v analog static consumption (no conversion) 300 * f periph a analog dynamic consumption (continuous conversion) 4ma
electrical characteri stics spc560b54x/6x 108/133 docid15131 rev 9 i dd_hv(flash) cc t cflash + dflash supply current on v dd_hv v dd = 5.5 v ? 12 ma i dd_hv(pll) cc t pll supply current on v dd_hv v dd = 5.5 v ? 30 * f periph a 1. operating conditions: t a = 25 c, f periph = 8 mhz to 64 mhz. 2. f periph is an absolute value. 3. during the conversion, the total current consumption is given from the sum of the static and dynamic consumption, i.e., (41 + 46) * f periph . table 47. on-chip peripherals current consumption (1) (continued) symbol c parameter conditions typical value (2) unit
spc560b54x/6x electrical characteristics docid15131 rev 9 109/133 4.18.2 dspi characteristics table 48. dspi characteristics (1) no. symbol c parameter dspi0/dspi1/dspi3/dspi5 dspi2/dspi4 unit min typ max min typ max 1t sck sr d sck cycle time master mode ? (mtfe = 0) 125 ? ? 333 ? ? ns d slave mode ? (mtfe = 0) 125 ? ? 333 ? ? d master mode ? (mtfe = 1) 83 ? ? 125 ? ? d slave mode ? (mtfe = 1) 83 ? ? 125 ? ? ?f dspi sr d dspi digital controller frequency ? ? f cpu ?? f cpu mhz ? ? t csc cc d internal delay between pad associated to sck and pad associated to csn in master mode for csn1->0 master mode ? ? 130 (2) ?? 15 (3) ns ? ? t asc cc d internal delay between pad associated to sck and pad associated to csn in master mode for csn1->1 master mode ? ? 130 (3) ? ? 130 (3) ns 2t cscext (4) sr d cs to sck delay slave mode 32 ? ? 32 ? ? ns 3t ascext (5) sr d after sck delay slave mode 1/f dspi + 5 ? ? 1/f dspi + 5 ? ? ns 4t sdc cc d sck duty cycle master mode ? t sck/2 ??t sck/2 ? ns sr d slave mode t sck/2 ?? t sck/2 ?? 5t a sr d slave access time slave mode ? ? 1/f dspi + 70 ? ? 1/f dspi + 130 ns 6t di sr d slave sout disable time slave mode 7 ? ? 7 ? ? ns 7t pcsc sr d pcsx to pcss time ? 0 ? ? 0 ? ? ns 8t pasc sr d pcss to pcsx time ? 0 ? ? 0 ? ? ns
electrical characteristics spc560b54x/6x 110/133 docid15131 rev 9 9t sui sr d data setup time for inputs master mode 43 ? ? 145 ? ? ns slave mode 5 ? ? 5 ? ? 10 t hi sr d data hold time for inputs master mode 0 ? ? 0 ? ? ns slave mode 2 (6) ?? 2 (6) ?? 11 t suo (7) cc d data valid after sck edge master mode ? ? 32 ? ? 50 ns slave mode ? ? 52 ? ? 160 12 t ho (7) cc d data hold time for outputs master mode 0 ? ? 0 ? ? ns slave mode 8 ? ? 13 ? ? 1. operating conditions: c l = 10 to 50 pf, slew in = 3.5 to 15 ns. 2. maximum value is reached when csn pad is configured as slow pad while sck pad is configured as medium. a positive value means that sck starts before csn is asserted. dspi2 has onl y slow sck available. 3. maximum value is reached when csn pad is configured as medium pad while sck pad is configured as slow. a positive value means that csn is deasserted before sck. dspi0 and dspi1 have onl y medium sck available. 4. the t csc delay value is configurable thro ugh a register. when configuring t csc (using pcssck and cssck fields in dspi_ctarx registers), delay between internal cs and internal sck must be higher than ? t csc to ensure positive t cscext . 5. the t asc delay value is configurable thr ough a register. when configuring t asc (using pasc and asc fields in dspi_ctarx registers), delay between internal cs and internal sck must be higher than ? t asc to ensure positive t ascext . 6. this delay value corresponds to smpl_pt = 00b which is bit field 9 and 8 of dspi_mcr register. 7. sck and sout are configured as medium pad. table 48. dspi characteristics (1) (continued) no. symbol c parameter dspi0/dspi1/dspi3/dspi5 dspi2/dspi4 unit min typ max min typ max
docid15131 rev 9 111/133 spc560b54x/6x electrical characteristics 132 figure 22. dspi classic spi timing ? master, cpha = 0 data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol = 0) (cpol = 1) 3 2 note: numbers shown reference table 47 .
electrical characteri stics spc560b54x/6x 112/133 docid15131 rev 9 figure 23. dspi classic spi timing ? master, cpha = 1 figure 24. dspi classic spi timing ? slave, cpha = 0 data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol = 0) (cpol = 1) note: numbers shown reference table 47 . last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) note: numbers shown reference table 47 .
docid15131 rev 9 113/133 spc560b54x/6x electrical characteristics 132 figure 25. dspi classic spi timing ? slave, cpha = 1 figure 26. dspi modified transfer format timing ? master, cpha = 0 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol = 0) (cpol = 1) note: numbers shown reference table 47 . pcsx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol = 0) (cpol = 1) note: numbers shown reference table 47 .
electrical characteri stics spc560b54x/6x 114/133 docid15131 rev 9 figure 27. dspi modified transfer format timing ? master, cpha = 1 figure 28. dspi modified transfer format timing ? slave, cpha = 0 pcsx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol = 0) (cpol = 1) note: numbers shown reference table 47 . last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) 12 note: numbers shown reference table 47 .
docid15131 rev 9 115/133 spc560b54x/6x electrical characteristics 132 figure 29. dspi modified transfer format timing ? slave, cpha = 1 figure 30. dspi pcs strobe (pcss ) timing 4.18.3 nexus characteristics 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol = 0) (cpol = 1) note: numbers shown reference table 47 . pcsx 7 8 pcss note: numbers shown reference table 47 . table 49. nexus characteristics no. symbol c parameter value unit min typ max 1t tcyc cc d tck cycle time 64 ? ? ns 2t mcyc cc d mcko cycle time 32 ? ? ns 3t mdov cc d mcko low to mdo data valid ? ? 8 ns 4t mseov cc d mcko low to mseo_b data valid ? ? 8 ns
electrical characteri stics spc560b54x/6x 116/133 docid15131 rev 9 figure 31. nexus tdi, tms, tdo timing 5t evtov cc d mcko low to evto data valid ? ? 8 ns 6 t ntdis cc d tdi data setup time 15 ? ? ns t ntmss cc d tms data setup time 15 ? ? ns 7 t ntdih cc d tdi data hold time 5 ? ? ns t ntmsh cc d tms data hold time 5 ? ? ns 8t tdov cc d tck low to tdo data valid 35 ? ? ns 9t tdoi cc d tck low to tdo data invalid 6 ? ? ns table 49. nexus characteristics (continued) no. symbol c parameter value unit min typ max 10 tck tms, tdi tdo 11 12 note: numbers shown reference table 49 .
docid15131 rev 9 117/133 spc560b54x/6x electrical characteristics 132 4.18.4 jtag characteristics figure 32. timing diagram ? jtag boundary scan table 50. jtag characteristics no. symbol c parameter value unit min typ max 1t jcyc cc d tck cycle time 64 ? ? ns 2t tdis cc d tdi setup time 15 ? ? ns 3t tdih cc d tdi hold time 5 ? ? ns 4t tmss cc d tms setup time 15 ? ? ns 5t tmsh cc d tms hold time 5 ? ? ns 6t tdov cc d tck low to tdo valid ? ? 33 ns 7t tdoi cc d tck low to tdo invalid 6 ? ? ns input data valid output data valid data inputs data outputs data outputs tck note: numbers shown reference table 50 . 3/5 2/4 7 6
package characteristics spc560b54x/6x 118/133 docid15131 rev 9 5 package characteristics 5.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. 5.2 package mechanical data 5.2.1 lqfp176 figure 33. lqfp176 package mechanical drawing
docid15131 rev 9 119/133 spc560b54x/6x package characteristics 132 table 51. lqfp176 mechanical data (1) symbol mm inches (2) min typ max min typ max a 1.400 ? 1.600 ? 0.063 a1 0.050 ? 0.150 0.002 ? a2 1.350 ? 1.450 0.053 ? 0.057 b 0.170 ? 0.270 0.007 ? 0.011 c 0.090 ? 0.200 0.004 ? 0.008 d 23.900 ? 24.100 0.941 ? 0.949 e 23.900 ? 24.100 0.941 ? 0.949 e ? 0.500 ? ? 0.020 ? hd 25.900 ? 26.100 1.020 ? 1.028 he 25.900 ? 26.100 1.020 ? 1.028 l (3) 0.450 ? 0.750 0.018 ? 0.030 l1 ? 1.000 ? ? 0.039 ? zd ? 1.250 ? ? 0.049 ? ze ? 1.250 ? ? 0.049 ? q 0 ? 7 0 ? 7 tolerance mm inches ccc 0.080 0.0031 1. controlling dimension: millimeter. 2. values in inches are converted from mm and rounded to 4 decimal digits. 3. l dimension is measured at gauge plane at 0.25 mm above the seating plane.
package characteristics spc560b54x/6x 120/133 docid15131 rev 9 5.2.2 lqfp144 figure 34. lqfp144 package mechanical drawing table 52. lqfp144 mechanical data symbol mm inches (1) min typ max min typ max a ? ? 1.600 ? ? 0.0630 a1 0.050 ? 0.150 0.0020 ? 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 ? 0.200 0.0035 ? 0.0079 d 21.800 22.000 22.200 0.8583 0.8661 0.8740
docid15131 rev 9 121/133 spc560b54x/6x package characteristics 132 d1 19.800 20.000 20.200 0.7795 0.7874 0.7953 d3 ? 17.500 ? ? 0.6890 ? e 21.800 22.000 22.200 0.8583 0.8661 0.8740 e1 19.800 20.000 20.200 0.7795 0.7874 0.7953 e3 ? 17.500 ? ? 0.6890 ? e ? 0.500 ? ? 0.0197 ? l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 ? 1.000 ? ? 0.0394 ? k 0.0 3.5 7.0 3.5 0.0 7.0 tolerance mm inches ccc 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 52. lqfp144 mechanical data (continued) symbol mm inches (1) min typ max min typ max
package characteristics spc560b54x/6x 122/133 docid15131 rev 9 5.2.3 lqfp100 figure 35. lqfp100 package mechanical drawing table 53. lqfp100 mechanical data symbol mm inches (1) min typ max min typ max a ? ? 1.600 ? ? 0.0630 a1 0.050 ? 0.150 0.0020 ? 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 ? 0.200 0.0035 ? 0.0079 d 15.800 16.000 16.200 0.6220 0.6299 0.6378 d1 13.800 14.000 14.200 0.5433 0.5512 0.5591 d3 ? 12.000 ? ? 0.4724 ? e 15.800 16.000 16.200 0.6220 0.6299 0.6378
docid15131 rev 9 123/133 spc560b54x/6x package characteristics 132 e1 13.800 14.000 14.200 0.5433 0.5512 0.5591 e3 ? 12.000 ? ? 0.4724 ? e ? 0.500 ? ? 0.0197 ? l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 ? 1.000 ? ? 0.0394 ? k 0.0 3.5 7.0 0.0 3.5 7.0 tolerance mm inches ccc 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 53. lqfp100 mechanical data (continued) symbol mm inches (1) min typ max min typ max
package characteristics spc560b54x/6x 124/133 docid15131 rev 9 5.2.4 lbga208 figure 36. lbga208 package mechanical drawing 1. the terminal a1 corner must be identified on the top surface by using a corner chamfer, ink or metalized markings, or other feature of package body or integral heatslug. ? a distinguishing feature is allowable on the bottom su rface of the package to identify the terminal a1 corner. exact shape of each corner is optional. 13 5 7 9111315 2 4 6 8 10 12 14 16 r l k t j n m p a b h g f d c e a1 corner index area (see note 1) bottom view b (208 balls) m m eee fff cab c seating plane a d d1 f e e1 f e a a1 a2 a3 a4 d ddd e b a c table 54. lbga208 mechanical data symbol mm inches (1) notes min typ max min typ max a ? ? 1.70 ? ? 0.0669 (2) a1 0.30 ? ? 0.0118 ? ? ? a2 ? 1.085 ? ? 0.0427 ? ? a3 ? 0.30 ? ? 0.0118 ? ? a4 ? ? 0.80 ? ? 0.0315 ? b 0.50 0.60 0.70 0.0197 0.0236 0.0276 (3)
docid15131 rev 9 125/133 spc560b54x/6x package characteristics 132 d 16.80 17.00 17.20 0.6614 0.6693 0.6772 ? d1 ? 15.00 ? ? 0.5906 ? ? e 16.80 17.00 17.20 0.6614 0.6693 0.6772 ? e1 ? 15.00 ? ? 0.5906 ? ? e ? 1.00 ? ? 0.0394 ? ? f ? 1.00 ? ? 0.0394 ? ? ddd ? ? 0.20 ? ? 0.0079 eee ? ? 0.25 ? ? 0.0098 (4) fff ? ? 0.10 ? ? 0.0039 (5) 1. values in inches are converted from mm and rounded to 4 decimal digits. 2. lbga stands for l ow profile b all g rid a rray. ? ? low profile: the total profile height (dim a) is m easured from the seating plane to the top of the component ? ? the maximum total package height is ca lculated by the following methodology: ? a2 (typ) + a1 (typ) + ?? (a1 2 + a3 2 + a4 2 tolerance values) ? ? low profile: 1.20 mm < a < 1.70 mm 3. the typical ball diameter before mounting is 0.60mm. 4. the tolerance of position that controls the location of the pattern of balls with respect to datums a and b. ? for each ball there is a cylindrical tole rance zone eee perpendicular to datum c and lo cated on true position with respect to datums a and b as defined by e. the axis perpendicular to dat um c of each ball must lie within this tolerance zone. 5. the tolerance of position that controls the location of the balls within the matrix with respect to each other. ? for each ball there is a cylindrical toler ance zone fff perpendicular to datum c and lo cated on true position as defined by e. the axis perpendicular to datum c of each bal l must lie within this tolerance zone. ? each tolerance zone fff in the array is cont ained entirely in the respective zone eee above. ? the axis of each ball mu st lie simultaneously in both tolerance zones. table 54. lbga208 mechanical data (continued) symbol mm inches (1) notes min typ max min typ max
ordering information spc560b54x/6x 126/133 docid15131 rev 9 6 ordering information figure 37. commercial product code structure 1. lbga208 is availabl e only as development package for nexus2+. memory packing core family y = tray ? x = tape and reel 90 ? 4e0 = 48 mhz eeprom 5v/3v ? 6e0 = 64 mhz eeprom 5v/3v ? b = ? 40 to 105c ? c = ? 40 to 125c ? l3 = lqfp100 ? l5 = lqfp144 ? l7 = lqfp176 ? b2 = lbga208 1 ? 64 = 1536 kb ? 60 = 1024 kb ? 54 = 768 kb ? b = body ? 0 = e200z0h ? spc56 = power architecture in 90nm temperature package custom vers. spc56 64 y 0b c l3 6e0 example code: product identifier
docid15131 rev 9 127/133 spc560b54x/6x abbreviations 132 appendix a abbreviations table 55 lists abbreviations used but not defined elsewhere in this document. table 55. abbreviations abbreviation meaning cmos complementary metal oxide semiconductor cpha clock phase cpol clock polarity cs peripheral chip select evto event out mcko message clock out mdo message data out mseo message start/end out mtfe modified timing format enable sck serial communications clock sout serial data out tbd to be defined tck test clock input tdi test data input tdo test data output tms test mode select
revision history spc560b54x/6x 128/133 docid15131 rev 9 revision history table 56 summarizes revisions to this document. table 56. revision history date revision changes 12-jan-2009 1 initial release 07-dec-2009 2 updated device summary-added lbga208 part number updated features replaced 27 irqs in place of 23 adc features external ballast resist or support conditions updated device summary-added 208 bga details updated block diagram to include wkup updated block diagram to include 5 ch adc 12 -bit updated block summary table updated lqfp 144, 176 and 100 pinouts. applied new naming convention for adc signals as adcx_p[x] and adcx_s[x] section 1, ?general description updated spc560b54/60/64 device comparison table updated block diagram-aligned with 512k updated block summary-aligned with 512k section 2, ?package pinouts updated 100,144,176,208 packages according to cut2.0 changes added section 3.5.1, ?external ballast resistor recommendations added nvusro [watchdog_en] field description updated absolute maximum ratings updated lqfp thermal characteristics updated i/o supply segments updated voltage regulator capacitance connection updated low voltage monitor el ectrical characteristics updated low voltage power domain electrical characteristics updated dc electrical characteristics updated program/erase specifications updated conversion characteristics (10 bit adc) updated fmpll electrical characteristics updated fast rc oscillator electric al characteristics-aligned with spc560b4x/b5x/c4x/c5x updated on-chip peripherals current consumption updated adc characteristics and error definitions diagram updated adc conversion characteristics (10 bit and 12 bit) added adc characteristics and error definitions diagram for 12 bit adc
docid15131 rev 9 129/133 spc560b54x/6x revision history 132 23-feb-2010 3 updated features updated block diagram to connect peripherals to pad i/o updated block summary to include adc 12-bit updated 144, 176 and 100 pinouts to adjust format issues table 26 flash module life-retention value changed from 1-5 to 5 yrs minor editing changes 13-sep-2010 4 editorial changes and improvements. cover page: removed lbga208 package silhouette updated ?features? section table 2 : updated footnote concerning lbga208 in the block diagram: ? added ?5ch 12-bit adc? block. ? updated legend. ? added ?interrupt request with wakeup functionality? as an input to the wkpu block. figure 2 : removed alternate functions figure 3 : removed alternate functions figure 4 : removed alternate functions table 3 : added contents concerning the following blocks: cmu, edma, ecsm, mc_me, mc_pcu, nmi, sscm, swt and wkpu added section 3.2, pin muxing section 4: electrical characteristics : removed ?caution? note section 4.2: nvusro register : removed ?nvusro[watchdog_en] field description? section table 12 : v in : removed min value in ?relative to v dd ? row table 13 ?tv dd : contents merged into one row ?v dd_bv : changed min value in ?relative to v dd ? row section 4.5: thermal characteristics ? section 4.5.1: external balla st resistor recommendations : added new paragraph about power supply ? table 15 : added r ? jb and r ? jc rows ? removed ?lbga208 thermal characteristics? table table 16 : rewrote parameter description of w fi and w nfi section 4.6.5: i/o pad current specification ? removed i dynseg information ? updated ?i/o supply segments? table table 23 : removed i dynseg row added table 24 table 56. revision history (continued) date revision changes
revision history spc560b54x/6x 130/133 docid15131 rev 9 13-sep-2010 4 (cont.) table 26 ? updated all values ? removed i vregref and i vredlvd12 rows ? added the footnote ?the duration of the in-rush current depends on the capacitance placed on lv pins. bv decaps must be sized accordingly. refer to imreg value for minimum amount of current to be provided in cc.? to the i dd_bv specification. table 27 ? updated v porh min/max value ? updated v lvdlvcorl min value updated table 28 table 29 ?t dwprogram : added initial max value ? inserted t eslat row table 30 : removed the ?to be confirmed? footnote in the ?crystal oscillator and resonat or connection scheme? figure, removed r p . table 40 ? removed g msxosc row ?i sxoscbias : added min/typ/max value table 41 : ? added f vco row ? added ? t stjit row table 42 ?i fircpwd : removed row for t a = 55 c ? updated t fircsu row table 45 : added two rows: i adc0pwd and i adc0run table 46 ? added two rows: i adc1pwd and i adc1run ? updated values of f adc_1 and t adc1_pu ? updated t adc1_c row updated table 47 updated table 48 added table 55 29-oct- 2010 5 removed ?preliminary?subject to change wi thout notice? marking. this data sheet contains specifications bas ed on characterization data. updated table 55 added table 56 updated figure 37 table 56. revision history (continued) date revision changes
docid15131 rev 9 131/133 spc560b54x/6x revision history 132 12-sep- 2011 6 editorial and formatting changes throughout replaced instances of ?e200z0? with ?e200z0h? device family comparison table: ? added 1 mb code flash lqfp100 version ? added 1.5 mb code flash lqfp144 version ? removed 768 kb code flash lqfp176 version ? changed linflex count for 144-pin lqfp?was ?6?; is ?8? ? changed linflex count for 176-pin lqfp?was ?8?; is ?10? ? replaced 105 c with 125 c in footnote 2 spc560b54/6x block diagram: added gpio and vreg to legend spc560b54/6x series block summary: added acronym ?jtagc?; in wkpu function changed ?up to 18 external sources? to ?up to 27 external sources? lqfp144 pin configuration: for pins 37?72, re stored the pin labels that existed prior to 27 july 2010 lqfp176 pin configuration: corrected na me of pin 4: was epc[15]; is pc[15] added following sections: ? pad configuration during reset phases ? pad configuration during standby mode exit ? voltage supply pins ? pad types ? system pins ? functional port pins ? nexus 2+ pins section ?nvusro register?: edited content to separate configuration into electrical parameters and digital functionality; updat ed footnote describing default value of ?1? in field descriptions nvusro[pad3v5v] and nvusro[oscillator_margin] added section ?nvusro[watchdog_en] field description? tables ?absolute maximum ratings? and ?reco mmended operating conditions (3.3 v)?: replaced ?vss_hv_adc0, vss_hv_adc1? with ?vdd_hv_adc0, vdd_hv_adc1? in v dd_adc parameter description ?recommended operating conditions (5.0 v)? table: replaced ?vss_hv_adc0, vss_hv_adc1? with ?vdd_hv_adc0, vdd_hv_adc1? in v dd_adc parameter description; changed 3.6v to 3.0v in footnote 2 section ?external ballast resistor recomm endations?: replaced ?low voltage monitor? with ?low voltage detector (lvd)? ?i/o input dc electrical charac teristics? table: updated i lkg characteristics ?medium configuration output buffer electrical characteristics? table: changed ?i oh = 100 a? to ?i ol = 100 a? in v ol conditions i/o weight: updated table (includes replac ing instances of bit ?sre? with ?src?) ?reset electrical characteristics? table: updated parameter classification for |i wpu | updated voltage regulator el ectrical characteristics section ?low voltage detector electrical c haracteristics?: changed title (was ?voltage monitor electrical characteristics?); changed ?as well as four low voltage detectors? to ?as well as five low voltage detectors?; added event status flag names found in rgm chapter of device reference manual to por module and lvd descriptions; replaced instances of ?low voltage monitor? with ?low voltage detector?; updated values for v lvdlvbkpl and v lvdlvcorl updated section ?power consumption? table 56. revision history (continued) date revision changes
revision history spc560b54x/6x 132/133 docid15131 rev 9 12-sep- 2011 (continued) 6 (continued) section ?program/erase characteristics?: removed table ?flash_biu settings vs. frequency of operation? and associated introduction ?program and erase specificat ions? table: updated symbols pfcrn settings vs. frequency of operation: replaced ?flash_biu? with ?pfcrn? in table title; updated field names and frequencies ?flash power supply dc electrical charac teristics? table: deleted footnote 2 crystal oscillator and resonator connection scheme: inserted footnote about possibly requiring a series resistor fast external crystal oscillator (4 to 16 mhz) electrical characteristics: updated parameter classification for v fxoscop slow external crystal oscillator (32 khz) electrical characteristics: updated footnote 1 section ?adc electrical characteristics?: upda ted symbols for offset error and gain error section ?input impedance and adc accuracy?: changed ?v a /v a2 ? to ?v a2 /v a ? in equation 11 adc input leakage current: updated i lkg characteristics adc_0 conversion characteristics table: replaced instances of ?adcx_conf_sample_input? with ?i npsamp?; replaced instances of ?adcx_conf_comp? with ?inpcmp adc_1 characteristic and error definitions: replaced ?avdd? with ?v dd_adc? adc_1 conversion characteristics table: replaced instances of ?adcx_conf_sample_input? with ?i npsamp?; replaced instances of ?adcx_conf_comp? with ?inpcmp? updated ?on-chip peripherals current consumption? table removed order codes tables. 18-sep-2013 7 updated disclaimer. 05-may-2014 8 table 13: recommended operating conditions (3.3 v) , added minimum value of t vdd and footnote about it. table 14: recommended operating conditions (5.0 v) , added minimum value of t vdd and footnote about it. table 21: output pin transition times , replaced t tr with t tr table 25: reset electrical characteristics , replaced t tr with t tr updated section 4.17.2: input impedance and adc accuracy table 27: low voltage detector electrical characteristics , changed v lvdhv3l (min) and v lvdhv3bl (min) from 2.7 v to 2.6 v. table 29: program and erase specifications , added footnote about t esrt table 41: fmpll electrical characteristics , deleted footnote relative to maximum value of f cpu table 45: adc_0 conversion characteristics (10-bit adc_0) , changed i adc0run value from 40 ma to 5 ma. table 48: dspi characteristics , in the heading row, replaced dspi0/dspi1/dspi5/dspi6 with dspi0/dspi1/dspi3/dspi5. 22-jan-2016 9 in table 1: device summary , added spc560b64l3 for 1.5 mb code flash devices. in table 2: spc560b54/6x family comparison , added column relating to ?lqfp100? package in spc560b64 devices. in table 28: power consumption on vdd_bv and vdd_hv : ? changed footnote 2 ?running consumpt ion does not include i/os...? to ?i ddmax is drawn only from the vdd_bv pin. running consumption does not include i/os...? ? changed footnote 4 ?run curre nt measured with...? to ?i ddrun is drawn only from the vdd_bv pin. run current measured with...? table 56. revision history (continued) date revision changes
docid15131 rev 9 133/133 spc560b54x/6x 133 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics ? all rights reserved

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